clock

[raggedstone] / ethernet / source / top.vhd

diff --git a/ethernet/source/top.vhd b/ethernet/source/top.vhd
index 68188ac8926d666474c85a3f4144045099621b22..184e744cddbf5d683298c32917e9cfe585fbd154 100644 (file)
--- a/ethernet/source/top.vhd
+++ b/ethernet/source/top.vhd
@@ -30,7 +30,9 @@ PORT(
         MCOLL_PAD_I : IN std_logic;
         MCRS_PAD_I : IN std_logic;
         MD_PAD_IO : INOUT std_logic;
-        MDC_PAD_O : OUT std_logic
+        MDC_PAD_O : OUT std_logic;
+
+       LED_2 : OUT std_logic
 );
 end ethernet;
 
@@ -152,6 +154,49 @@ PORT(
         );
 END COMPONENT;
 
+COMPONENT eth_cop
+PORT(
+       wb_clk_i : IN std_logic;
+       wb_rst_i : IN std_logic;
+       m1_wb_adr_i : IN std_logic_vector(31 downto 0);
+       m1_wb_sel_i : IN std_logic_vector(3 downto 0);
+       m1_wb_we_i : IN std_logic;
+       m1_wb_dat_i : IN std_logic_vector(31 downto 0);
+       m1_wb_cyc_i : IN std_logic;
+       m1_wb_stb_i : IN std_logic;
+       m2_wb_adr_i : IN std_logic_vector(31 downto 0);
+       m2_wb_sel_i : IN std_logic_vector(3 downto 0);
+       m2_wb_we_i : IN std_logic;
+       m2_wb_dat_i : IN std_logic_vector(31 downto 0);
+       m2_wb_cyc_i : IN std_logic;
+       m2_wb_stb_i : IN std_logic;
+       s1_wb_ack_i : IN std_logic;
+       s1_wb_err_i : IN std_logic;
+       s1_wb_dat_i : IN std_logic_vector(31 downto 0);
+       s2_wb_ack_i : IN std_logic;
+       s2_wb_err_i : IN std_logic;
+       s2_wb_dat_i : IN std_logic_vector(31 downto 0);          
+       m1_wb_dat_o : OUT std_logic_vector(31 downto 0);
+       m1_wb_ack_o : OUT std_logic;
+       m1_wb_err_o : OUT std_logic;
+       m2_wb_dat_o : OUT std_logic_vector(31 downto 0);
+       m2_wb_ack_o : OUT std_logic;
+       m2_wb_err_o : OUT std_logic;
+       s1_wb_adr_o : OUT std_logic_vector(31 downto 0);
+       s1_wb_sel_o : OUT std_logic_vector(3 downto 0);
+       s1_wb_we_o : OUT std_logic;
+       s1_wb_cyc_o : OUT std_logic;
+       s1_wb_stb_o : OUT std_logic;
+       s1_wb_dat_o : OUT std_logic_vector(31 downto 0);
+       s2_wb_adr_o : OUT std_logic_vector(31 downto 0);
+       s2_wb_sel_o : OUT std_logic_vector(3 downto 0);
+       s2_wb_we_o : OUT std_logic;
+       s2_wb_cyc_o : OUT std_logic;
+       s2_wb_stb_o : OUT std_logic;
+       s2_wb_dat_o : OUT std_logic_vector(31 downto 0)
+       );
+END COMPONENT;
+
 signal pci_rst_o : std_logic;
 signal pci_rst_oe_o : std_logic;
 signal pci_inta_o : std_logic;
@@ -232,6 +277,8 @@ end generate;
 
 wb_adr_i <= wbm_adr_o (11 downto 2);
 
+wb_clk_i <= PCI_CLOCK;
+
 Inst_pci_bridge32: pci_bridge32 PORT MAP(
         wb_clk_i => wb_clk_i ,
         wb_rst_i => '0',
@@ -328,7 +375,7 @@ Inst_eth_top: eth_top PORT MAP(
         mtx_clk_pad_i => MTX_CLK_PAD_I,
         mtxd_pad_o => MTXD_PAD_O,
         mtxen_pad_o => MTXEN_PAD_O,
-        -- mtxerr_pad_o => ,
+        mtxerr_pad_o => LED_2,
         mrx_clk_pad_i => MRX_CLK_PAD_I,
         mrxd_pad_i => MRXD_PAD_I,
         mrxdv_pad_i => MRXDV_PAD_I,
@@ -344,4 +391,45 @@ Inst_eth_top: eth_top PORT MAP(
         int_o => int_o
 );
 
+--Inst_eth_cop: eth_cop PORT MAP(
+--     wb_clk_i => ,
+--     wb_rst_i => ,
+--     m1_wb_adr_i => ,
+--     m1_wb_sel_i => ,
+--     m1_wb_we_i => ,
+--     m1_wb_dat_o => ,
+--     m1_wb_dat_i => ,
+--     m1_wb_cyc_i => ,
+--     m1_wb_stb_i => ,
+--     m1_wb_ack_o => ,
+--     m1_wb_err_o => ,
+--     m2_wb_adr_i => ,
+--     m2_wb_sel_i => ,
+--     m2_wb_we_i => ,
+--     m2_wb_dat_o => ,
+--     m2_wb_dat_i => ,
+--     m2_wb_cyc_i => ,
+--     m2_wb_stb_i => ,
+--     m2_wb_ack_o => ,
+--     m2_wb_err_o => ,
+--     s1_wb_adr_o => ,
+--     s1_wb_sel_o => ,
+--     s1_wb_we_o => ,
+--     s1_wb_cyc_o => ,
+--     s1_wb_stb_o => ,
+--     s1_wb_ack_i => ,
+--     s1_wb_err_i => ,
+--     s1_wb_dat_i => ,
+--     s1_wb_dat_o => ,
+--     s2_wb_adr_o => ,
+--     s2_wb_sel_o => ,
+--     s2_wb_we_o => ,
+--     s2_wb_cyc_o => ,
+--     s2_wb_stb_o => ,
+--     s2_wb_ack_i => ,
+--     s2_wb_err_i => ,
+--     s2_wb_dat_i => ,
+--     s2_wb_dat_o => 
+--);
+
 end architecture ethernet_arch;