update edk project to 10.1

[raggedstone] / heartbeat / source / heartbeat.vhd

diff --git a/heartbeat/source/heartbeat.vhd b/heartbeat/source/heartbeat.vhd
index cae72cd9a4e4f6042fa4cac8a6a5647e8f26e0cc..03180ef0af5ee631ab1a9842584b1c3047f1e386 100644 (file)
--- a/heartbeat/source/heartbeat.vhd
+++ b/heartbeat/source/heartbeat.vhd
@@ -27,15 +27,15 @@ architecture rtl of heartbeat is
 begin
 
 process(clk_i, nrst_i)
 begin
 
 process(clk_i, nrst_i)

-variable counter : std_logic_vector(31 downto 0);
+variable counter : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";

 variable state : std_logic_vector(7 downto 0) := "00000001";
 variable direction : std_logic := '0';
 begin
 
 if (rising_edge(clk_i)) then
 variable state : std_logic_vector(7 downto 0) := "00000001";
 variable direction : std_logic := '0';
 begin
 
 if (rising_edge(clk_i)) then

-       if nrst_i = '0' then
-               counter := (others => '0');
-        else
+--     if nrst_i = '0' then
+--             counter := (others => '0');
+--        else

                led2_o <= state(0);
                led3_o <= state(1);
                led4_o <= state(2);
                led2_o <= state(0);
                led3_o <= state(1);
                led4_o <= state(2);


@@ -46,7 +46,7 @@ if (rising_edge(clk_i)) then
                led9_o <= state(7);
                counter := counter + 1;
                if counter = divider then
                led9_o <= state(7);
                counter := counter + 1;
                if counter = divider then

-                       if state(7) = '1' then
+                       if state(3) = '1' then

                                direction := '1';
                        end if;
 
                                direction := '1';
                        end if;
 


@@ -63,7 +63,7 @@ if (rising_edge(clk_i)) then
                        end if;
                        counter := (others => '0');
                end if;
                        end if;
                        counter := (others => '0');
                end if;

-       end if;
+--     end if;

 end if;
 end process;
 end architecture;
 end if;
 end process;
 end architecture;