first import of dhwk.

[raggedstone] / dhwk / source / parity_out.vhd

diff --git a/dhwk/source/parity_out.vhd b/dhwk/source/parity_out.vhd
new file mode 100644 (file)
index 0000000..285764d
--- /dev/null
+++ b/dhwk/source/parity_out.vhd
@@ -0,0 +1,66 @@
+-- J.STELZNER\r
+-- INFORMATIK-3 LABOR\r
+-- 23.08.2006\r
+-- File: PARITY_OUT.VHD\r
+\r
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+\r
+entity PARITY_OUT is\r
+       port(\r
+               PCI_CLOCK               :in             std_logic;\r
+               PCI_RSTn                :in             std_logic;\r
+               PAR_IN                  :in             std_logic_vector ( 2 downto 0); \r
+               PAR_REG                 :in             std_logic;\r
+               SERR_CHECK      :in             std_logic;      \r
+               PERR_CHECK      :in             std_logic;\r
+               OE_PCI_PAR      :in             std_logic;\r
+               OE_PCI_PERR     :in             std_logic;\r
+               PA_ER_RE                :in             std_logic;\r
+               SERR_ENA                :in             std_logic;\r
+               PCI_PAR_IN      :in             std_logic;\r
+               PERR                            :out    std_logic;\r
+               SERR                            :out    std_logic;\r
+               PCI_PERRn               :out    std_logic;      --      s/t/s\r
+               PCI_SERRn               :out    std_logic;      --      o/d\r
+               PCI_PAR                 :out    std_logic               --      t/s\r
+               );\r
+end entity PARITY_OUT; \r
+\r
+architecture PARITY_OUT_DESIGN of PARITY_OUT is\r
+\r
+       signal PAR                      :std_logic;\r
+       signal PAR_FF           :std_logic;\r
+       signal SERR_FF  :std_logic;\r
+       signal PERR_FF  :std_logic;\r
+  \r
+begin\r
+\r
+       PAR             <= ( PAR_IN(2) xor PAR_IN(1) xor PAR_IN(0) ); \r
+\r
+       process (PCI_CLOCK, PCI_RSTn) \r
+       begin\r
+               if      PCI_RSTn = '0'  then    PAR_FF  <= '0';\r
+                                                                                                                       PERR_FF <= '0';\r
+                                                                                                                       SERR_FF <= '0'; \r
+\r
+               elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
+\r
+                       PAR_FF  <=      PAR;\r
+                       SERR_FF <=      ((PCI_PAR_IN xor PAR) and SERR_CHECK) and PA_ER_RE and SERR_ENA and (not SERR_FF);   \r
+                       PERR_FF <=      ((PCI_PAR_IN xor PAR) and PERR_CHECK) and (not PERR_FF);  \r
+\r
+               end if;\r
+       end process; \r
+\r
+       SERR                    <=  SERR_FF;\r
+       PERR                    <=  PERR_FF;\r
+\r
+       PCI_PAR         <= PAR_FF                               when    OE_PCI_PAR      = '1' else 'Z' ; \r
+       PCI_SERRn       <= '0'                                  when    SERR_FF                 = '1' else 'Z' ;\r
+       PCI_PERRn       <= not PERR_FF  when    OE_PCI_PERR     = '1' and PA_ER_RE = '1' else 'Z' ;\r
+\r
+end architecture PARITY_OUT_DESIGN;\r
+\r
+\r
+\r