first import of dhwk.

[raggedstone] / dhwk / source / synplify.vhd

diff --git a/dhwk/source/synplify.vhd b/dhwk/source/synplify.vhd
new file mode 100644 (file)
index 0000000..904bf0d
--- /dev/null
+++ b/dhwk/source/synplify.vhd
@@ -0,0 +1,184 @@
+-----------------------------------------------------------------------------\r
+--                                                                         --\r
+-- Copyright (c) 1997 by Synplicity, Inc.  All rights reserved.            --\r
+--                                                                         --\r
+-- This source file may be used and distributed without restriction        --\r
+-- provided that this copyright statement is not removed from the file     --\r
+-- and that any derivative work contains this copyright notice.            --\r
+--                                                                         --\r
+-- Primitive library for post synthesis simulation                         --\r
+-- These models are not intended for efficient synthesis                   --\r
+--                                                                         --\r
+-----------------------------------------------------------------------------\r
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+entity prim_counter is\r
+    generic (w : integer := 8);\r
+    port (\r
+        q : buffer std_logic_vector(w - 1 downto 0);\r
+        cout : out std_logic;\r
+        d : in std_logic_vector(w - 1 downto 0);\r
+        cin : in std_logic;\r
+        clk : in std_logic;\r
+        rst : in std_logic;\r
+        load : in std_logic;\r
+        en : in std_logic;\r
+        updn : in std_logic\r
+    );\r
+end prim_counter;\r
+\r
+architecture beh of prim_counter is\r
+    signal nextq : std_logic_vector(w - 1 downto 0);\r
+begin\r
+    nxt: process (q, cin, updn)\r
+        variable i : integer;\r
+        variable nextc, c : std_logic;\r
+    begin\r
+        nextc := cin;\r
+        for i in 0 to w - 1 loop\r
+            c := nextc;\r
+            nextq(i) <= c xor (not updn) xor q(i);\r
+            nextc := (c and (not updn)) or \r
+                 (c and q(i)) or\r
+                 ((not updn) and q(i));\r
+        end loop;\r
+        cout <= nextc;\r
+    end process;\r
+\r
+    ff : process (clk, rst)\r
+    begin\r
+        if rst = '1' then\r
+            q <= (others => '0');\r
+        elsif rising_edge(clk) then\r
+            q <= nextq;\r
+        end if;\r
+    end process ff;\r
+end beh;\r
+\r
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+entity prim_dff is\r
+    port (q : out std_logic;\r
+          d : in std_logic;\r
+          clk : in std_logic;\r
+          r : in std_logic := '0';\r
+          s : in std_logic := '0');\r
+end prim_dff;\r
+\r
+architecture beh of prim_dff is\r
+begin\r
+    ff : process (clk, r, s)\r
+    begin\r
+        if r = '1' then\r
+            q <= '0';\r
+        elsif s = '1' then\r
+            q <= '1';\r
+        elsif rising_edge(clk) then\r
+            q <= d;\r
+        end if;\r
+    end process ff;\r
+end beh;\r
+\r
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+entity prim_latch is\r
+    port (q : out std_logic;\r
+          d : in std_logic;\r
+          clk : in std_logic;\r
+          r : in std_logic := '0';\r
+          s : in std_logic := '0');\r
+end prim_latch;\r
+\r
+architecture beh of prim_latch is\r
+begin\r
+    q <= '0' when r = '1' else\r
+         '1' when s = '1' else\r
+         d when clk = '1';\r
+end beh;\r
+\r
+\r
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.std_logic_unsigned.all;\r
+\r
+entity prim_ramd is\r
+generic (\r
+   data_width : integer := 4;\r
+    addr_width : integer := 5);\r
+port (\r
+    dout : out std_logic_vector(data_width-1 downto 0);\r
+    aout : in std_logic_vector(addr_width-1 downto 0);\r
+    din  : in std_logic_vector(data_width-1 downto 0);\r
+    ain : in std_logic_vector(addr_width-1 downto 0);\r
+    we   : in std_logic;\r
+    clk  : in std_logic);\r
+end prim_ramd;\r
+\r
+architecture beh of prim_ramd is\r
+\r
+constant depth : integer := 2** addr_width;\r
+type mem_type is array (depth-1 downto 0) of std_logic_vector (data_width-1 downto 0);\r
+signal mem: mem_type;\r
+\r
+begin  \r
+\r
+dout <= mem(conv_integer(aout));\r
+\r
+process (clk)\r
+    begin\r
+        if rising_edge(clk) then    \r
+            if (we = '1') then\r
+                mem(conv_integer(ain)) <= din;\r
+            end if;\r
+        end if;\r
+end process;\r
+\r
+end beh ;\r
+\r
+\r
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+package components is\r
+    component prim_counter\r
+        generic (w : integer);\r
+        port (\r
+            q : buffer std_logic_vector(w - 1 downto 0);\r
+            cout : out std_logic;\r
+            d : in std_logic_vector(w - 1 downto 0);\r
+            cin : in std_logic;\r
+            clk : in std_logic;\r
+            rst : in std_logic;\r
+            load : in std_logic;\r
+            en : in std_logic;\r
+            updn : in std_logic\r
+        );\r
+    end component;\r
+    component prim_dff\r
+        port (q : out std_logic;\r
+              d : in std_logic;\r
+              clk : in std_logic;\r
+              r : in std_logic := '0';\r
+              s : in std_logic := '0');\r
+    end component;\r
+    component prim_latch\r
+        port (q : out std_logic;\r
+              d : in std_logic;\r
+              clk : in std_logic;\r
+              r : in std_logic := '0';\r
+              s : in std_logic := '0');\r
+    end component;\r
+\r
+    component prim_ramd is\r
+    generic (\r
+        data_width : integer := 4;\r
+        addr_width : integer := 5);\r
+    port (\r
+        dout : out std_logic_vector(data_width-1 downto 0);\r
+        aout : in std_logic_vector(addr_width-1 downto 0);\r
+        din  : in std_logic_vector(data_width-1 downto 0);\r
+        ain : in std_logic_vector(addr_width-1 downto 0);\r
+        we   : in std_logic;\r
+        clk  : in std_logic);\r
+    end component;\r
+\r
+end components;\r