--- /dev/null
+-- VHDL model created from schematic user_io.sch -- Jan 09 09:34:12 2007\r
+\r
+\r
+\r
+LIBRARY ieee;\r
+\r
+USE ieee.std_logic_1164.ALL;\r
+USE ieee.numeric_std.ALL;\r
+\r
+\r
+entity USER_IO is\r
+ Port ( AD_REG : In std_logic_vector (31 downto 0);\r
+ ADDR_REG : In std_logic_vector (31 downto 0);\r
+ CBE_REGn : In std_logic_vector (3 downto 0);\r
+ FLAG : In std_logic_vector (7 downto 0);\r
+ INT_REG : In std_logic_vector (7 downto 0);\r
+ IO_WR_COM : In std_logic;\r
+ IRDY_REGn : In std_logic;\r
+ PCI_CLK : In std_logic;\r
+ R_FIFO_Q : In std_logic_vector (7 downto 0);\r
+ READ_SEL : In std_logic_vector (1 downto 0);\r
+ TRDYn : In std_logic;\r
+ READ_XX1_0 : Out std_logic;\r
+ READ_XX3_2 : Out std_logic;\r
+ READ_XX5_4 : Out std_logic;\r
+ READ_XX7_6 : Out std_logic;\r
+ REG_OUT_XX0 : Out std_logic_vector (7 downto 0);\r
+ REG_OUT_XX6 : Out std_logic_vector (7 downto 0);\r
+ REG_OUT_XX7 : Out std_logic_vector (7 downto 0);\r
+ USER_DATA_OUT : Out std_logic_vector (31 downto 0);\r
+ WRITE_XX1_0 : Out std_logic;\r
+ WRITE_XX3_2 : Out std_logic;\r
+ WRITE_XX5_4 : Out std_logic;\r
+ WRITE_XX7_6 : Out std_logic );\r
+end USER_IO;\r
+\r
+architecture SCHEMATIC of USER_IO is\r
+\r
+ SIGNAL gnd : std_logic := '0';\r
+ SIGNAL vcc : std_logic := '1';\r
+\r
+ signal WRITE_XX1_0_DUMMY : std_logic;\r
+ signal WRITE_XX7_6_DUMMY : std_logic;\r
+ signal REG_OUT_XX7_DUMMY : std_logic_vector (7 downto 0);\r
+ signal REG_OUT_XX6_DUMMY : std_logic_vector (7 downto 0);\r
+ signal REG_OUT_XX0_DUMMY : std_logic_vector (7 downto 0);\r
+\r
+ component IO_WR_SEL\r
+ Port ( ADDR_REG : In std_logic_vector (31 downto 0);\r
+ CBE_REGn : In std_logic_vector (3 downto 0);\r
+ IO_WR_COM : In std_logic;\r
+ IRDY_REGn : In std_logic;\r
+ TRDYn : In std_logic;\r
+ WRITE_XX1_0 : Out std_logic;\r
+ WRITE_XX3_2 : Out std_logic;\r
+ WRITE_XX5_4 : Out std_logic;\r
+ WRITE_XX7_6 : Out std_logic );\r
+ end component;\r
+\r
+ component DATA_MUX\r
+ Port ( ADDR_REG : In std_logic_vector (31 downto 0);\r
+ CBE_REGn : In std_logic_vector (3 downto 0);\r
+ MUX_IN_XX0 : In std_logic_vector (7 downto 0);\r
+ MUX_IN_XX1 : In std_logic_vector (7 downto 0);\r
+ MUX_IN_XX2 : In std_logic_vector (7 downto 0);\r
+ MUX_IN_XX3 : In std_logic_vector (7 downto 0);\r
+ MUX_IN_XX4 : In std_logic_vector (7 downto 0);\r
+ MUX_IN_XX5 : In std_logic_vector (7 downto 0);\r
+ MUX_IN_XX6 : In std_logic_vector (7 downto 0);\r
+ MUX_IN_XX7 : In std_logic_vector (7 downto 0);\r
+ READ_SEL : In std_logic_vector (1 downto 0);\r
+ MUX_OUT : Out std_logic_vector (31 downto 0);\r
+ READ_XX1_0 : Out std_logic;\r
+ READ_XX3_2 : Out std_logic;\r
+ READ_XX5_4 : Out std_logic;\r
+ READ_XX7_6 : Out std_logic );\r
+ end component;\r
+\r
+ component REG_IO\r
+ Port ( AD_REG : In std_logic_vector (31 downto 0);\r
+ PCI_CLOCK : In std_logic;\r
+ RESET : In std_logic;\r
+ WRITE_XX1_0 : In std_logic;\r
+ WRITE_XX7_6 : In std_logic;\r
+ REG_OUT_XX0 : Out std_logic_vector (7 downto 0);\r
+ REG_OUT_XX6 : Out std_logic_vector (7 downto 0);\r
+ REG_OUT_XX7 : Out std_logic_vector (7 downto 0) );\r
+ end component;\r
+\r
+begin\r
+\r
+ REG_OUT_XX0 <= REG_OUT_XX0_DUMMY;\r
+ REG_OUT_XX6 <= REG_OUT_XX6_DUMMY;\r
+ REG_OUT_XX7 <= REG_OUT_XX7_DUMMY;\r
+ WRITE_XX7_6 <= WRITE_XX7_6_DUMMY;\r
+ WRITE_XX1_0 <= WRITE_XX1_0_DUMMY;\r
+\r
+ I4 : IO_WR_SEL\r
+ Port Map ( ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),\r
+ CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),\r
+ IO_WR_COM=>IO_WR_COM, IRDY_REGn=>IRDY_REGn,\r
+ TRDYn=>TRDYn, WRITE_XX1_0=>WRITE_XX1_0_DUMMY,\r
+ WRITE_XX3_2=>WRITE_XX3_2, WRITE_XX5_4=>WRITE_XX5_4,\r
+ WRITE_XX7_6=>WRITE_XX7_6_DUMMY );\r
+ I2 : DATA_MUX\r
+ Port Map ( ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),\r
+ CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),\r
+ MUX_IN_XX0(7 downto 0)=>REG_OUT_XX0_DUMMY(7 downto 0),\r
+ MUX_IN_XX1(7 downto 0)=>FLAG(7 downto 0),\r
+ MUX_IN_XX2(7 downto 0)=>R_FIFO_Q(7 downto 0),\r
+ MUX_IN_XX3(7 downto 0)=>FLAG(7 downto 0),\r
+ MUX_IN_XX4(7 downto 0)=>INT_REG(7 downto 0),\r
+ MUX_IN_XX5(7 downto 0)=>FLAG(7 downto 0),\r
+ MUX_IN_XX6(7 downto 0)=>REG_OUT_XX6_DUMMY(7 downto 0),\r
+ MUX_IN_XX7(7 downto 0)=>REG_OUT_XX7_DUMMY(7 downto 0),\r
+ READ_SEL(1 downto 0)=>READ_SEL(1 downto 0),\r
+ MUX_OUT(31 downto 0)=>USER_DATA_OUT(31 downto 0),\r
+ READ_XX1_0=>READ_XX1_0, READ_XX3_2=>READ_XX3_2,\r
+ READ_XX5_4=>READ_XX5_4, READ_XX7_6=>READ_XX7_6 );\r
+ I1 : REG_IO\r
+ Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),\r
+ PCI_CLOCK=>PCI_CLK, RESET=>REG_OUT_XX7_DUMMY(0),\r
+ WRITE_XX1_0=>WRITE_XX1_0_DUMMY,\r
+ WRITE_XX7_6=>WRITE_XX7_6_DUMMY,\r
+ REG_OUT_XX0(7 downto 0)=>REG_OUT_XX0_DUMMY(7 downto 0),\r
+ REG_OUT_XX6(7 downto 0)=>REG_OUT_XX6_DUMMY(7 downto 0),\r
+ REG_OUT_XX7(7 downto 0)=>REG_OUT_XX7_DUMMY(7 downto 0) );\r
+\r
+end SCHEMATIC;\r
projects / raggedstone / blobdiff