move config space header into pci core directory

[raggedstone] / dhwk / source / Io_reg.vhd

diff --git a/dhwk/source/Io_reg.vhd b/dhwk/source/Io_reg.vhd
index f56df31169a6910ee33ee1f3aa217ddbd27b772f..ecbd9d67dbdbae908d0cc8cad8947b66e2361736 100644 (file)
--- a/dhwk/source/Io_reg.vhd
+++ b/dhwk/source/Io_reg.vhd
@@ -1,74 +1,71 @@
--- J.STELZNER\r
--- INFORMATIK-3 LABOR\r
--- 23.08.2006\r
--- File: IO_MUX.VHD\r
-\r
-library ieee;\r
-use ieee.std_logic_1164.all;\r
-\r
-entity IO_REG is\r
-    port\r
-       (\r
-       PCI_CLOCK               :in             std_logic;\r
-       PCI_RSTn                :in             std_logic;\r
-       PCI_FRAMEn      :in             std_logic;\r
-       PCI_IRDYn               :in             std_logic;\r
-       PCI_IDSEL               :in             std_logic;\r
-       PCI_PAR                 :in             std_logic;\r
-       PCI_CBEn                :in             std_logic_vector ( 3 downto 0);\r
-       OE_PCI_AD               :in             std_logic;\r
-       IO_DATA                 :in             std_logic_vector (31 downto 0);\r
-       AD_REG                  :out    std_logic_vector (31 downto 0);\r
-       CBE_REGn                :out    std_logic_vector ( 3 downto 0);\r
-       FRAME_REGn      :out    std_logic;      \r
-       IRDY_REGn               :out    std_logic;      \r
-       IDSEL_REG               :out    std_logic;\r
-       PAR_REG                 :out    std_logic;              \r
-       PCI_AD                  :out    std_logic_vector (31 downto 0)  --      t/s\r
-    );\r
-end entity IO_REG;\r
-\r
-architecture IO_REG_DESIGN of IO_REG is\r
-\r
-       signal  REG_AD                  :std_logic_vector (31 downto 0); \r
-       signal  REG_CBEn                :std_logic_vector ( 3 downto 0);\r
-       signal  REG_FRAMEn      :std_logic;\r
-       signal  REG_IRDYn               :std_logic;\r
-       signal  REG_IDSEL               :std_logic;\r
-       signal  REG_PAR                 :std_logic;\r
-\r
-begin \r
-\r
-       process (PCI_CLOCK, PCI_RSTn) \r
-       begin\r
-               if      PCI_RSTn = '0'  then\r
-\r
-                       REG_AD                  <= X"00000000";\r
-                       REG_CBEn                <= "0000";\r
-                       REG_FRAMEn      <= '1';\r
-                       REG_IRDYn               <= '1';\r
-                       REG_IDSEL               <= '0';\r
-                       REG_PAR                 <= '0';\r
-\r
-               elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
-\r
-                       REG_AD                  <=      IO_DATA;\r
-                       REG_CBEn                <=      PCI_CBEn;\r
-                       REG_FRAMEn      <=      PCI_FRAMEn;\r
-                       REG_IRDYn               <=      PCI_IRDYn;\r
-                       REG_IDSEL               <=      PCI_IDSEL;\r
-                       REG_PAR                 <=      PCI_PAR;\r
-\r
-               end if;\r
-       end process;\r
-\r
-       PCI_AD                  <=      REG_AD when OE_PCI_AD ='1' else (others => 'Z');\r
-\r
-       AD_REG                  <=      REG_AD;\r
-       CBE_REGn                <=      REG_CBEn;\r
-       FRAME_REGn      <=      REG_FRAMEn;\r
-       IRDY_REGn               <=      REG_IRDYn;\r
-       IDSEL_REG               <=      REG_IDSEL;\r
-       PAR_REG                 <=      REG_PAR;\r
-\r
-end architecture IO_REG_DESIGN;\r
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: IO_MUX.VHD
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity IO_REG is
+        port
+        (
+                PCI_CLOCK :in std_logic;
+                PCI_RSTn :in std_logic;
+                PCI_FRAMEn :in std_logic;
+                PCI_IRDYn :in std_logic;
+                PCI_IDSEL :in std_logic;
+                PCI_PAR :in std_logic;
+                PCI_CBEn :in std_logic_vector ( 3 downto 0);
+                OE_PCI_AD :in std_logic;
+                IO_DATA :in std_logic_vector (31 downto 0);
+                AD_REG :out std_logic_vector (31 downto 0);
+                CBE_REGn :out std_logic_vector ( 3 downto 0);
+                FRAME_REGn :out std_logic;
+                IRDY_REGn :out std_logic;
+                IDSEL_REG :out std_logic;
+                PAR_REG :out std_logic;
+                PCI_AD :out std_logic_vector (31 downto 0) -- t/s
+        );
+end entity IO_REG;
+
+architecture IO_REG_DESIGN of IO_REG is
+
+        signal REG_AD :std_logic_vector (31 downto 0);
+        signal REG_CBEn :std_logic_vector ( 3 downto 0);
+        signal REG_FRAMEn :std_logic;
+        signal REG_IRDYn :std_logic;
+        signal REG_IDSEL :std_logic;
+        signal REG_PAR :std_logic;
+
+begin
+
+        process (PCI_CLOCK, PCI_RSTn)
+        begin
+                if PCI_RSTn = '0' then
+                        REG_AD <= X"00000000";
+                        REG_CBEn <= "0000";
+                        REG_FRAMEn <= '1';
+                        REG_IRDYn <= '1';
+                        REG_IDSEL <= '0';
+                        REG_PAR <= '0';
+
+                elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then
+                        REG_AD <= IO_DATA;
+                        REG_CBEn <= PCI_CBEn;
+                        REG_FRAMEn <= PCI_FRAMEn;
+                        REG_IRDYn <= PCI_IRDYn;
+                        REG_IDSEL <= PCI_IDSEL;
+                        REG_PAR <= PCI_PAR;
+                end if;
+        end process;
+
+        PCI_AD <= REG_AD when OE_PCI_AD ='1' else (others => 'Z');
+
+        AD_REG <= REG_AD;
+        CBE_REGn <= REG_CBEn;
+        FRAME_REGn <= REG_FRAMEn;
+        IRDY_REGn <= REG_IRDYn;
+        IDSEL_REG <= REG_IDSEL;
+        PAR_REG <= REG_PAR;
+
+end architecture IO_REG_DESIGN;