identing

[raggedstone] / dhwk / source / Io_mux.vhd

diff --git a/dhwk/source/Io_mux.vhd b/dhwk/source/Io_mux.vhd
index ba27f4a4395565b5dd89faf75f4fcc48a3742649..14dc42e70616d7ccbb937f8acf5b12c3cd807be2 100644 (file)
--- a/dhwk/source/Io_mux.vhd
+++ b/dhwk/source/Io_mux.vhd
@@ -1,36 +1,36 @@
--- J.STELZNER\r
--- INFORMATIK-3 LABOR\r
--- 23.08.2006\r
--- File: IO_MUX.VHD\r
-\r
-library IEEE;\r
-use IEEE.std_logic_1164.all;\r
-\r
-entity IO_MUX is\r
-       port\r
-       (\r
-       READ_SEL                        :in             std_logic_vector ( 1 downto 0);\r
-       USER_DATA                       :in             std_logic_vector (31 downto 0);\r
-       CONFIG_DATA             :in             std_logic_vector (31 downto 0);\r
-       PCI_AD                          :in             std_logic_vector (31 downto 0);\r
-       IO_DATA                         :out    std_logic_vector (31 downto 0)\r
-       );\r
-end entity IO_MUX;\r
-\r
-architecture IO_MUX_DESIGN of IO_MUX is\r
-\r
-       signal  MUX             :std_logic_vector (31 downto 0); \r
-\r
-begin \r
-\r
-       MUX     <=      PCI_AD                  when    READ_SEL        =       "00"    else    -- WRITE_CONFIG \r
-                                       PCI_AD                  when    READ_SEL        =       "01"    else    -- WRITE_IO\r
-                                       CONFIG_DATA     when    READ_SEL        =       "10"    else    -- READ_CONFIG \r
-                                       USER_DATA               when    READ_SEL        =       "11"    else    -- READ_IO      \r
-                                       CONFIG_DATA;\r
-\r
---                                     MUX;\r
-\r
-       IO_DATA <= MUX;\r
-\r
-end architecture IO_MUX_DESIGN;\r
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: IO_MUX.VHD
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity IO_MUX is
+        port
+        (
+                READ_SEL :in std_logic_vector ( 1 downto 0);
+                USER_DATA :in std_logic_vector (31 downto 0);
+                CONFIG_DATA :in std_logic_vector (31 downto 0);
+                PCI_AD :in std_logic_vector (31 downto 0);
+                IO_DATA :out std_logic_vector (31 downto 0)
+        );
+end entity IO_MUX;
+
+architecture IO_MUX_DESIGN of IO_MUX is
+
+        signal MUX :std_logic_vector (31 downto 0);
+
+begin
+
+        MUX <= PCI_AD when READ_SEL = "00" else -- WRITE_CONFIG
+               PCI_AD when READ_SEL = "01" else -- WRITE_IO
+               CONFIG_DATA when READ_SEL = "10" else -- READ_CONFIG
+               USER_DATA when READ_SEL = "11" else -- READ_IO
+               CONFIG_DATA;
+
+ -- MUX;
+
+        IO_DATA <= MUX;
+
+end architecture IO_MUX_DESIGN;