identing

[raggedstone] / dhwk / source / config_mux_0.vhd

diff --git a/dhwk/source/config_mux_0.vhd b/dhwk/source/config_mux_0.vhd
index 64e2560bc1ff786977651c383372193cbeb3f3fc..f1b34f73217e5531e3e8a5fe2fa221514930ec28 100644 (file)
--- a/dhwk/source/config_mux_0.vhd
+++ b/dhwk/source/config_mux_0.vhd
@@ -1,44 +1,43 @@
--- J.STELZNER\r
--- INFORMATIK-3 LABOR\r
--- 23.08.2006\r
--- File: CONFIG_MUX_0.VHD\r
-\r
-library IEEE;\r
-use IEEE.std_logic_1164.all;\r
-\r
-entity CONFIG_MUX_0 is\r
-       port\r
-       (\r
-       READ_SEL                        :in             std_logic_vector( 2 downto 0);\r
-       CONF_DATA_00H   :in             std_logic_vector(31 downto 0);\r
-       CONF_DATA_04H   :in             std_logic_vector(31 downto 0);\r
-       CONF_DATA_08H   :in             std_logic_vector(31 downto 0);\r
-       CONF_DATA_10H   :in             std_logic_vector(31 downto 0);\r
-       CONF_DATA_3CH   :in             std_logic_vector(31 downto 0);\r
---CONF_DATA_40H        :in             std_logic_vector(31 downto 0);\r
-       CONF_DATA                       :out    std_logic_vector(31 downto 0)\r
-    );\r
-end entity CONFIG_MUX_0;\r
-\r
-architecture CONFIG_MUX_0_DESIGN of CONFIG_MUX_0 is\r
-\r
-       signal  MUX     :std_logic_vector (31 downto  0); \r
-\r
-begin\r
-\r
---*******************************************************************\r
---******************* PCI Read  Config-MUX **************************\r
---*******************************************************************\r
-\r
-       MUX <=  CONF_DATA_00H   when READ_SEL <= "000" else \r
-                                       CONF_DATA_04H   when READ_SEL <= "001" else\r
-                                       CONF_DATA_08H   when READ_SEL <= "010" else\r
-                                       CONF_DATA_10H   when READ_SEL <= "011" else\r
-                                       CONF_DATA_3CH   when READ_SEL <= "100" else\r
---                             CONF_DATA_40H   when READ_SEL <= "101" else\r
-                                       X"00000000"     ;\r
-\r
-       CONF_DATA <= MUX ;\r
-\r
-\r
-end architecture CONFIG_MUX_0_DESIGN;\r
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: CONFIG_MUX_0.VHD
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity CONFIG_MUX_0 is
+        port
+        (
+                READ_SEL :in std_logic_vector( 2 downto 0);
+                CONF_DATA_00H :in std_logic_vector(31 downto 0);
+                CONF_DATA_04H :in std_logic_vector(31 downto 0);
+                CONF_DATA_08H :in std_logic_vector(31 downto 0);
+                CONF_DATA_10H :in std_logic_vector(31 downto 0);
+                CONF_DATA_3CH :in std_logic_vector(31 downto 0);
+                --CONF_DATA_40H :in std_logic_vector(31 downto 0);
+                CONF_DATA :out std_logic_vector(31 downto 0)
+        );
+end entity CONFIG_MUX_0;
+
+architecture CONFIG_MUX_0_DESIGN of CONFIG_MUX_0 is
+
+        signal MUX :std_logic_vector (31 downto 0);
+
+begin
+
+ --*******************************************************************
+ --******************* PCI Read Config-MUX **************************
+ --*******************************************************************
+
+        MUX <= CONF_DATA_00H when READ_SEL <= "000" else
+               CONF_DATA_04H when READ_SEL <= "001" else
+               CONF_DATA_08H when READ_SEL <= "010" else
+               CONF_DATA_10H when READ_SEL <= "011" else
+               CONF_DATA_3CH when READ_SEL <= "100" else
+               -- CONF_DATA_40H when READ_SEL <= "101" else
+               X"00000000";
+
+        CONF_DATA <= MUX;
+
+end architecture CONFIG_MUX_0_DESIGN;