process (PCI_CLOCK)
begin
- if (rising_edge(PCI_CLOCK)) then
+ if (PCI_CLOCK'event and PCI_CLOCK = '1') then
if SIG_LOAD = '1' then
REG <= S_FIFO_Q_OUT;
process (PCI_CLOCK)
begin
- if (rising_edge(PCI_CLOCK)) then
+ if (PCI_CLOCK'event and PCI_CLOCK = '1') then
if RESET = '1' then
STATES <= S0;