lot of new files

[raggedstone] / dhwk / source / pci / pci_interface.vhd

diff --git a/dhwk/source/pci/pci_interface.vhd b/dhwk/source/pci/pci_interface.vhd
index d15f9da8412f4e1dfe95dee7c48484d855c3a1cb..722cce6dde2ce77956fed8992ed83024289beeeb 100644 (file)
--- a/dhwk/source/pci/pci_interface.vhd
+++ b/dhwk/source/pci/pci_interface.vhd
@@ -109,6 +109,12 @@ architecture SCHEMATIC of PCI_INTERFACE is
                        SERR : Out std_logic );
         end component;
 
+        component VERGLEICH
+                Port ( IN_A : In std_logic_vector (31 downto 0);
+                       IN_B : In std_logic_vector (31 downto 0);
+                       GLEICH_OUT : Out std_logic );
+        end component;
+
         component IO_MUX_REG
                 Port ( CONFIG_DATA : In std_logic_vector (31 downto 0);
                        LOAD_ADDR_REG : In std_logic;
@@ -183,6 +189,10 @@ begin
                    SERR_CHECK=>SERR_CHECK, SERR_ENA=>CONF_DATA_04H(8),
                    PCI_PAR=>PCI_PAR, PCI_PERRn=>PCI_PERRn,
                    PCI_SERRn=>PCI_SERRn, PERR=>PERR, SERR=>SERR );
+        I4 : VERGLEICH
+        Port Map ( IN_A(31 downto 0)=>CONF_DATA_10H(31 downto 0),
+        IN_B(31 downto 0)=>AD_REG_DUMMY(31 downto 0),
+        GLEICH_OUT=>MY_ADDR );
         I2 : IO_MUX_REG
         Port Map ( CONFIG_DATA(31 downto 0)=>CONF_DATA(31 downto 0),
                    LOAD_ADDR_REG=>LAR,
@@ -212,17 +222,4 @@ begin
         CONF_DATA_04H(31 downto 0)=>CONF_DATA_04H(31 downto 0),
         CONF_DATA_10H(31 downto 0)=>CONF_DATA_10H(31 downto 0) );
 
-        process (PCI_CLOCK,PCI_RSTn)
-        begin
-        if PCI_RSTn = '0' then
-                MY_ADDR <= '0';
-
-        elsif (rising_edge(PCI_CLOCK)) then
-                if (CONF_DATA_10H(31 downto 2) = ADDR_REG_DUMMY(31 downto 2)) then
-                        MY_ADDR <= '1';
-                else
-                        MY_ADDR <= '0';
-                end if;
-        end if;
-        end process;
 end SCHEMATIC;