signal IO_DATA : std_logic_vector (31 downto 0);\r
signal AD_REG_DUMMY : std_logic_vector (31 downto 0);\r
\r
- component ADDR_REGI\r
+ component ADDRESS_REGISTER\r
Port ( AD_REG : In std_logic_vector (31 downto 0);\r
LOAD_ADDR_REG : In std_logic;\r
PCI_CLOCK : In std_logic;\r
\r
AD_REG <= AD_REG_DUMMY;\r
\r
- I5 : ADDR_REGI\r
+ I5 : ADDRESS_REGISTER\r
Port Map ( AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),\r
LOAD_ADDR_REG=>LOAD_ADDR_REG, PCI_CLOCK=>PCI_CLOCK,\r
PCI_RSTn=>PCI_RSTn,\r