move address register

[raggedstone] / dhwk / source / io_mux_reg.vhd

diff --git a/dhwk/source/io_mux_reg.vhd b/dhwk/source/io_mux_reg.vhd
index 38f23567a5158f9b6d11bd76ae978dbb8ccf5b95..564d8bb6337261c42158713b19f5a112ff6d2cc2 100644 (file)
--- a/dhwk/source/io_mux_reg.vhd
+++ b/dhwk/source/io_mux_reg.vhd
@@ -38,7 +38,7 @@ architecture SCHEMATIC of IO_MUX_REG is
    signal  IO_DATA : std_logic_vector (31 downto 0);\r
    signal AD_REG_DUMMY : std_logic_vector (31 downto 0);\r
 \r
-   component ADDR_REGI\r
+   component ADDRESS_REGISTER\r
       Port (  AD_REG : In    std_logic_vector (31 downto 0);\r
              LOAD_ADDR_REG : In    std_logic;\r
              PCI_CLOCK : In    std_logic;\r
@@ -77,7 +77,7 @@ begin
 \r
    AD_REG <= AD_REG_DUMMY;\r
 \r
-   I5 : ADDR_REGI\r
+   I5 : ADDRESS_REGISTER\r
       Port Map ( AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),\r
                  LOAD_ADDR_REG=>LOAD_ADDR_REG, PCI_CLOCK=>PCI_CLOCK,\r
                  PCI_RSTn=>PCI_RSTn,\r