MD_PAD_IO : INOUT std_logic;
MDC_PAD_O : OUT std_logic;
+ PHY_CLOCK : OUT std_logic;
+
LED_2 : OUT std_logic
);
end ethernet;
);
end component;
+component phydcm is
+port ( CLKIN_IN : in std_logic;
+ RST_IN : in std_logic;
+ CLKFX_OUT : out std_logic;
+ CLK0_OUT : out std_logic;
+ LOCKED_OUT : out std_logic);
+end component;
+
signal pci_rst_o : std_logic;
signal pci_rst_oe_o : std_logic;
signal pci_inta_o : std_logic;
PCI_CBEn(i) <= pci_cbe_o(i) when (pci_cbe_oe_o(i) = '1') else 'Z';
end generate;
-wb_adr_i(11 downto 2) <= (others => '0');
-wb_adr_i <= wbm_adr_o (7 downto 2);
+wb_adr_i(11 downto 8) <= (others => '0');
+wb_adr_i(7 downto 2) <= wbm_adr_o (7 downto 2);
wb_clk_i <= PCI_CLOCK;
trig0 => trig0
);
+eth_dcm : phydcm
+port map (
+ CLKIN_IN => PCI_CLOCK,
+ RST_IN => not PCI_RSTn,
+ CLKFX_OUT => PHY_CLOCK,
+ CLK0_OUT => open,
+ LOCKED_OUT => open
+ );
+
end architecture ethernet_arch;