a bit better
[raggedstone] / ethernet / ethernet.prj
index 8b9a4542efb80ffb234fa866f3adc37d6dfa4b0b..869bd188c40fd0a58c37f7474b3fe3adad5fb4f0 100644 (file)
@@ -1,86 +1,88 @@
-vhdl work "source/ethernet/eth_crc.v"
-vhdl work "source/ethernet/eth_cop.v"
-vhdl work "source/ethernet/eth_maccontrol.v"
-vhdl work "source/ethernet/eth_register.v"
-vhdl work "source/ethernet/eth_fifo.v"
-vhdl work "source/ethernet/eth_rxstatem.v"
-vhdl work "source/ethernet/eth_txcounters.v"
-vhdl work "source/ethernet/eth_random.v"
-vhdl work "source/ethernet/eth_rxcounters.v"
-vhdl work "source/ethernet/eth_top.v"
-vhdl work "source/ethernet/eth_shiftreg.v"
-vhdl work "source/ethernet/eth_miim.v"
-vhdl work "source/ethernet/eth_wishbone.v"
-vhdl work "source/ethernet/eth_rxaddrcheck.v"
-vhdl work "source/ethernet/xilinx_dist_ram_16x32.v"
-vhdl work "source/ethernet/eth_spram_256x32.v"
-vhdl work "source/ethernet/eth_txethmac.v"
-vhdl work "source/ethernet/timescale.v"
-vhdl work "source/ethernet/eth_registers.v"
-vhdl work "source/ethernet/eth_defines.v"
-vhdl work "source/ethernet/eth_rxethmac.v"
-vhdl work "source/ethernet/eth_receivecontrol.v"
-vhdl work "source/ethernet/eth_outputcontrol.v"
-vhdl work "source/ethernet/eth_txstatem.v"
-vhdl work "source/ethernet/eth_transmitcontrol.v"
-vhdl work "source/ethernet/eth_macstatus.v"
-vhdl work "source/ethernet/eth_clockgen.v"
-vhdl work "source/pci/pci_target_unit.v"
-vhdl work "source/pci/pci_target32_stop_crit.v"
-vhdl work "source/pci/pci_delayed_sync.v"
-vhdl work "source/pci/pci_wb_slave_unit.v"
-vhdl work "source/pci/pci_frame_load_crit.v"
-vhdl work "source/pci/pci_mas_ad_en_crit.v"
-vhdl work "source/pci/pci_constants.v"
-vhdl work "source/pci/pci_wbw_wbr_fifos.v"
-vhdl work "source/pci/pci_wb_slave.v"
-vhdl work "source/pci/pci_target32_trdy_crit.v"
-vhdl work "source/pci/pci_target32_interface.v"
-vhdl work "source/pci/pci_wbw_fifo_control.v"
-vhdl work "source/pci/pci_wb_tpram.v"
-vhdl work "source/pci/pci_par_crit.v"
-vhdl work "source/pci/pci_conf_space.v"
-vhdl work "source/pci/pci_target32_sm.v"
-vhdl work "source/pci/pci_pciw_pcir_fifos.v"
-vhdl work "source/pci/pci_serr_en_crit.v"
-vhdl work "source/pci/pci_target32_devs_crit.v"
-vhdl work "source/pci/pci_out_reg.v"
-vhdl work "source/pci/pci_mas_ad_load_crit.v"
-vhdl work "source/pci/pci_delayed_write_reg.v"
-vhdl work "source/pci/pci_wbs_wbb3_2_wbb2.v"
-vhdl work "source/pci/pci_wb_master.v"
-vhdl work "source/pci/bus_commands.v"
-vhdl work "source/pci/pci_rst_int.v"
-vhdl work "source/pci/pci_sync_module.v"
-vhdl work "source/pci/pci_master32_sm_if.v"
-vhdl work "source/pci/pci_frame_crit.v"
-vhdl work "source/pci/pci_user_constants.v"
-vhdl work "source/pci/pci_io_mux_ad_load_crit.v"
-vhdl work "source/pci/pci_pciw_fifo_control.v"
-vhdl work "source/pci/pci_parity_check.v"
-vhdl work "source/pci/pci_irdy_out_crit.v"
-vhdl work "source/pci/pci_perr_crit.v"
-vhdl work "source/pci/pci_mas_ch_state_crit.v"
-vhdl work "source/pci/pci_spoci_ctrl.v"
-vhdl work "source/pci/pci_wb_addr_mux.v"
-vhdl work "source/pci/pci_perr_en_crit.v"
-vhdl work "source/pci/pci_target32_clk_en.v"
-vhdl work "source/pci/timescale.v"
-vhdl work "source/pci/pci_serr_crit.v"
-vhdl work "source/pci/pci_frame_en_crit.v"
-vhdl work "source/pci/pci_master32_sm.v"
-vhdl work "source/pci/pci_pci_tpram.v"
-vhdl work "source/pci/pci_cur_out_reg.v"
-vhdl work "source/pci/pci_io_mux.v"
-vhdl work "source/pci/pci_wbr_fifo_control.v"
-vhdl work "source/pci/pci_ram_16x40d.v"
-vhdl work "source/pci/pci_io_mux_ad_en_crit.v"
-vhdl work "source/pci/pci_async_reset_flop.v"
-vhdl work "source/pci/pci_wb_decoder.v"
-vhdl work "source/pci/pci_conf_cyc_addr_dec.v"
-vhdl work "source/pci/pci_bridge32.v"
-vhdl work "source/pci/pci_synchronizer_flop.v"
-vhdl work "source/pci/pci_pcir_fifo_control.v"
-vhdl work "source/pci/pci_cbe_en_crit.v"
-vhdl work "source/pci/pci_pci_decoder.v"
-vhdl work "source/pci/pci_in_reg.v"
+verilog work "source/ethernet/eth_crc.v"
+verilog work "source/ethernet/eth_cop.v"
+verilog work "source/ethernet/eth_maccontrol.v"
+verilog work "source/ethernet/eth_register.v"
+verilog work "source/ethernet/eth_fifo.v"
+verilog work "source/ethernet/eth_rxstatem.v"
+verilog work "source/ethernet/eth_txcounters.v"
+verilog work "source/ethernet/eth_random.v"
+verilog work "source/ethernet/eth_rxcounters.v"
+verilog work "source/ethernet/eth_top.v"
+verilog work "source/ethernet/eth_shiftreg.v"
+verilog work "source/ethernet/eth_miim.v"
+verilog work "source/ethernet/eth_wishbone.v"
+verilog work "source/ethernet/eth_rxaddrcheck.v"
+verilog work "source/ethernet/xilinx_dist_ram_16x32.v"
+verilog work "source/ethernet/eth_spram_256x32.v"
+verilog work "source/ethernet/eth_txethmac.v"
+verilog work "source/ethernet/timescale.v"
+verilog work "source/ethernet/eth_registers.v"
+verilog work "source/ethernet/eth_defines.v"
+verilog work "source/ethernet/eth_rxethmac.v"
+verilog work "source/ethernet/eth_receivecontrol.v"
+verilog work "source/ethernet/eth_outputcontrol.v"
+verilog work "source/ethernet/eth_txstatem.v"
+verilog work "source/ethernet/eth_transmitcontrol.v"
+verilog work "source/ethernet/eth_macstatus.v"
+verilog work "source/ethernet/eth_clockgen.v"
+verilog work "source/pci/pci_target_unit.v"
+verilog work "source/pci/pci_target32_stop_crit.v"
+verilog work "source/pci/pci_delayed_sync.v"
+verilog work "source/pci/pci_wb_slave_unit.v"
+verilog work "source/pci/pci_frame_load_crit.v"
+verilog work "source/pci/pci_mas_ad_en_crit.v"
+verilog work "source/pci/pci_constants.v"
+verilog work "source/pci/pci_wbw_wbr_fifos.v"
+verilog work "source/pci/pci_wb_slave.v"
+verilog work "source/pci/pci_target32_trdy_crit.v"
+verilog work "source/pci/pci_target32_interface.v"
+verilog work "source/pci/pci_wbw_fifo_control.v"
+verilog work "source/pci/pci_wb_tpram.v"
+verilog work "source/pci/pci_par_crit.v"
+verilog work "source/pci/pci_conf_space.v"
+verilog work "source/pci/pci_target32_sm.v"
+verilog work "source/pci/pci_pciw_pcir_fifos.v"
+verilog work "source/pci/pci_serr_en_crit.v"
+verilog work "source/pci/pci_target32_devs_crit.v"
+verilog work "source/pci/pci_out_reg.v"
+verilog work "source/pci/pci_mas_ad_load_crit.v"
+verilog work "source/pci/pci_delayed_write_reg.v"
+verilog work "source/pci/pci_wbs_wbb3_2_wbb2.v"
+verilog work "source/pci/pci_wb_master.v"
+verilog work "source/pci/bus_commands.v"
+verilog work "source/pci/pci_rst_int.v"
+verilog work "source/pci/pci_sync_module.v"
+verilog work "source/pci/pci_master32_sm_if.v"
+verilog work "source/pci/pci_frame_crit.v"
+verilog work "source/pci/pci_user_constants.v"
+verilog work "source/pci/pci_io_mux_ad_load_crit.v"
+verilog work "source/pci/pci_pciw_fifo_control.v"
+verilog work "source/pci/pci_parity_check.v"
+verilog work "source/pci/pci_irdy_out_crit.v"
+verilog work "source/pci/pci_perr_crit.v"
+verilog work "source/pci/pci_mas_ch_state_crit.v"
+verilog work "source/pci/pci_spoci_ctrl.v"
+verilog work "source/pci/pci_wb_addr_mux.v"
+verilog work "source/pci/pci_perr_en_crit.v"
+verilog work "source/pci/pci_target32_clk_en.v"
+verilog work "source/pci/timescale.v"
+verilog work "source/pci/pci_serr_crit.v"
+verilog work "source/pci/pci_frame_en_crit.v"
+verilog work "source/pci/pci_master32_sm.v"
+verilog work "source/pci/pci_pci_tpram.v"
+verilog work "source/pci/pci_cur_out_reg.v"
+verilog work "source/pci/pci_io_mux.v"
+verilog work "source/pci/pci_wbr_fifo_control.v"
+verilog work "source/pci/pci_ram_16x40d.v"
+verilog work "source/pci/pci_io_mux_ad_en_crit.v"
+verilog work "source/pci/pci_async_reset_flop.v"
+verilog work "source/pci/pci_wb_decoder.v"
+verilog work "source/pci/pci_conf_cyc_addr_dec.v"
+verilog work "source/pci/pci_bridge32.v"
+verilog work "source/pci/pci_synchronizer_flop.v"
+verilog work "source/pci/pci_pcir_fifo_control.v"
+verilog work "source/pci/pci_cbe_en_crit.v"
+verilog work "source/pci/pci_pci_decoder.v"
+verilog work "source/pci/pci_in_reg.v"
+vhdl work "source/top.vhd"
+vhdl work "source/phydcm.vhd"
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