update to EDK 9.1i

[raggedstone] / ethernet / source / pci / pci_user_constants.v

diff --git a/ethernet/source/pci/pci_user_constants.v b/ethernet/source/pci/pci_user_constants.v
index 22ef572a11510086778b5040c9021301e7f13b96..70c9b0e9a36dc170b29b5bb73b0f7ce9f1fb2e19 100644 (file)
--- a/ethernet/source/pci/pci_user_constants.v
+++ b/ethernet/source/pci/pci_user_constants.v
@@ -39,7 +39,13 @@
 // CVS Revision History
 //
 // $Log: pci_user_constants.v,v $
-// Revision 1.1  2007-03-20 17:50:56  sithglan
+// Revision 1.3  2007-03-21 11:53:06  sithglan
+// enable address translation
+//
+// Revision 1.2  2007/03/20 20:56:19  sithglan
+// changes
+//
+// Revision 1.1  2007/03/20 17:50:56  sithglan
 // add shit
 //
 // Revision 1.15  2004/08/19 15:27:34  mihad
@@ -111,8 +117,8 @@
 `define PCIW_ADDR_LENGTH 3
 `define PCIR_ADDR_LENGTH 3
 
-//`define FPGA
-//`define XILINX
+`define FPGA
+`define XILINX
 
 `define WB_RAM_DONT_SHARE
 `define PCI_RAM_DONT_SHARE
@@ -137,8 +143,8 @@
 
 // these two defines allow user to select active high or low output enables on PCI bus signals, depending on
 // output buffers instantiated. Xilinx FPGAs use active low output enables.
-`define ACTIVE_LOW_OE
-//`define ACTIVE_HIGH_OE
+// `define ACTIVE_LOW_OE
+`define ACTIVE_HIGH_OE
 
 // HOST/GUEST implementation selection - see design document and specification for description of each implementation
 // only one can be defined at same time
@@ -278,7 +284,7 @@
 // addresses will pass through bridge unchanged, regardles of address translation enable bits.
 // Address translation also slows down the decoding
 //When  ADDR_TRAN_IMPL this define is present then adress translation is enabled after reset.
-//`define ADDR_TRAN_IMPL
+`define ADDR_TRAN_IMPL
 
 // decode speed for WISHBONE definition - initial cycle on WISHBONE bus will take 1 WS for FAST, 2 WSs for MEDIUM and 3 WSs for slow.
 // slower decode speed can be used, to provide enough time for address to be decoded.