only regenerate cores when needed, and not on every build

[raggedstone] / ethernet / ila.xco

diff --git a/ethernet/ila.xco b/ethernet/ila.xco
deleted file mode 100644 (file)
index 713d6d6..0000000
--- a/ethernet/ila.xco
+++ /dev/null
@@ -1,115 +0,0 @@
-# BEGIN Project Options
-SET addpads = False
-SET asysymbol = False
-SET busformat = BusFormatAngleBracketNotRipped
-SET createndf = False
-SET designentry = VHDL
-SET device = xc3s1500
-SET devicefamily = spartan3
-SET flowvendor = Other
-SET formalverification = False
-SET foundationsym = False
-SET implementationfiletype = Ngc
-SET package = fg456
-SET removerpms = False
-SET simulationfiles = Structural
-SET speedgrade = -4
-SET verilogsim = False
-SET vhdlsim = True
-# END Project Options
-# BEGIN Select
-SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.02.a
-# END Select
-# BEGIN Parameters
-CSET component_name=ila
-CSET counter_width_1=Disabled
-CSET counter_width_10=Disabled
-CSET counter_width_11=Disabled
-CSET counter_width_12=Disabled
-CSET counter_width_13=Disabled
-CSET counter_width_14=Disabled
-CSET counter_width_15=Disabled
-CSET counter_width_16=Disabled
-CSET counter_width_2=Disabled
-CSET counter_width_3=Disabled
-CSET counter_width_4=Disabled
-CSET counter_width_5=Disabled
-CSET counter_width_6=Disabled
-CSET counter_width_7=Disabled
-CSET counter_width_8=Disabled
-CSET counter_width_9=Disabled
-CSET data_port_width=64
-CSET data_same_as_trigger=false
-CSET enable_storage_qualification=true
-CSET enable_trigger_output_port=false
-CSET exclude_from_data_storage_1=true
-CSET exclude_from_data_storage_10=true
-CSET exclude_from_data_storage_11=true
-CSET exclude_from_data_storage_12=true
-CSET exclude_from_data_storage_13=true
-CSET exclude_from_data_storage_14=true
-CSET exclude_from_data_storage_15=true
-CSET exclude_from_data_storage_16=true
-CSET exclude_from_data_storage_2=true
-CSET exclude_from_data_storage_3=true
-CSET exclude_from_data_storage_4=true
-CSET exclude_from_data_storage_5=true
-CSET exclude_from_data_storage_6=true
-CSET exclude_from_data_storage_7=true
-CSET exclude_from_data_storage_8=true
-CSET exclude_from_data_storage_9=true
-CSET match_type_1=basic
-CSET match_type_10=basic
-CSET match_type_11=basic
-CSET match_type_12=basic
-CSET match_type_13=basic
-CSET match_type_14=basic
-CSET match_type_15=basic
-CSET match_type_16=basic
-CSET match_type_2=basic
-CSET match_type_3=basic
-CSET match_type_4=basic
-CSET match_type_5=basic
-CSET match_type_6=basic
-CSET match_type_7=basic
-CSET match_type_8=basic
-CSET match_type_9=basic
-CSET match_units_1=1
-CSET match_units_10=1
-CSET match_units_11=1
-CSET match_units_12=1
-CSET match_units_13=1
-CSET match_units_14=1
-CSET match_units_15=1
-CSET match_units_16=1
-CSET match_units_2=1
-CSET match_units_3=1
-CSET match_units_4=1
-CSET match_units_5=1
-CSET match_units_6=1
-CSET match_units_7=1
-CSET match_units_8=1
-CSET match_units_9=1
-CSET max_sequence_levels=1
-CSET number_of_trigger_ports=1
-CSET sample_data_depth=2048
-CSET sample_on=Rising
-CSET trigger_port_width_1=32
-CSET trigger_port_width_10=8
-CSET trigger_port_width_11=8
-CSET trigger_port_width_12=8
-CSET trigger_port_width_13=8
-CSET trigger_port_width_14=8
-CSET trigger_port_width_15=8
-CSET trigger_port_width_16=8
-CSET trigger_port_width_2=8
-CSET trigger_port_width_3=8
-CSET trigger_port_width_4=8
-CSET trigger_port_width_5=8
-CSET trigger_port_width_6=8
-CSET trigger_port_width_7=8
-CSET trigger_port_width_8=8
-CSET trigger_port_width_9=8
-CSET use_rpms=true
-# END Parameters
-GENERATE