wb_clk_i <= PCI_CLOCK;
data(31 downto 0) <= wbm_adr_o;
-data(40 downto 33) <= wbm_adr_o (7 downto 0);
-data(41) <= MD_PAD_IO;
-data(42) <= md_pad_o;
-data(43) <= md_padoe_o;
-data(44) <= mdc_pad_o_watch;
+data(39 downto 32) <= wbm_adr_o (7 downto 0);
+data(40) <= MD_PAD_IO;
+data(41) <= md_pad_o;
+data(42) <= md_padoe_o;
+data(43) <= mdc_pad_o_watch;
+data(44) <= pci_inta_o;
MDC_PAD_O <= mdc_pad_o_watch;
data(63 downto 45) <= (others => '0');