- port
- (
- IO_WR_COM :in std_logic;
- IRDY_REGn :in std_logic;
- TRDYn :in std_logic;
- ADDR_REG :in std_logic_vector(31 downto 0);
- CBE_REGn :in std_logic_vector( 3 downto 0);
- WRITE_XX1_0 :out std_logic;
- WRITE_XX3_2 :out std_logic;
- WRITE_XX5_4 :out std_logic;
- WRITE_XX7_6 :out std_logic
- );
+ port
+ (
+ IO_WR_COM :in std_logic;
+ IRDY_REGn :in std_logic;
+ TRDYn :in std_logic;
+ ADDR_REG :in std_logic_vector(31 downto 0);
+ CBE_REGn :in std_logic_vector( 3 downto 0);
+ WRITE_XX1_0 :out std_logic;
+ WRITE_XX3_2 :out std_logic;
+ WRITE_XX5_4 :out std_logic;
+ WRITE_XX7_6 :out std_logic
+ );
- ADDR <= ADDR_REG(3) & ADDR_REG(2) & CBE_REGn;
+ WRITE_XX1_0 <= '1' when WR_ENA = '1' and ADDR = "001100" else '0';
+ WRITE_XX3_2 <= '1' when WR_ENA = '1' and ADDR = "000011" else '0';
+ WRITE_XX5_4 <= '1' when WR_ENA = '1' and ADDR = "011100" else '0';
+ WRITE_XX7_6 <= '1' when WR_ENA = '1' and ADDR = "010011" else '0';
-
- WRITE_XX1_0 <= '1' when WR_ENA = '1' and ADDR = "001100" else '0';
- WRITE_XX3_2 <= '1' when WR_ENA = '1' and ADDR = "000011" else '0';
- WRITE_XX5_4 <= '1' when WR_ENA = '1' and ADDR = "011100" else '0';
- WRITE_XX7_6 <= '1' when WR_ENA = '1' and ADDR = "010011" else '0';
-