move config space header into pci core directory

[raggedstone] / dhwk / source / MESS_1_TB.vhd

diff --git a/dhwk/source/MESS_1_TB.vhd b/dhwk/source/MESS_1_TB.vhd
index 4476632a8d29d973cf50eb5d5a5ea6b72e132d65..ec9b512c3c042bfcf04fa4e5a2a57e322ccdee6d 100644 (file)
--- a/dhwk/source/MESS_1_TB.vhd
+++ b/dhwk/source/MESS_1_TB.vhd
@@ -7,27 +7,27 @@ library IEEE;
 use IEEE.std_logic_1164.all;
 
 entity MESS_1_TB is
-       port
-       (
-       KONST_1                         :in             std_logic;
-       PCI_IDSEL                       :in             std_logic;
-       DEVSELn                         :in             std_logic;
-       INTAn                                   :in             std_logic;
-       REG_OUT_XX7             :in             std_logic_vector(7 downto 0);
-       TB_PCI_IDSEL    :out    std_logic;
-       TB_DEVSELn              :out    std_logic;
-       TB_INTAn                        :out    std_logic
-       );
+        port
+        (
+                KONST_1 :in std_logic;
+                PCI_IDSEL :in std_logic;
+                DEVSELn :in std_logic;
+                INTAn :in std_logic;
+                REG_OUT_XX7 :in std_logic_vector(7 downto 0);
+                TB_PCI_IDSEL :out std_logic;
+                TB_DEVSELn :out std_logic;
+                TB_INTAn :out std_logic
+        );
 end entity MESS_1_TB;
 
 architecture MESS_1_TB_DESIGN of MESS_1_TB is
- 
+
 begin
 
-       TB_PCI_IDSEL    <=      PCI_IDSEL       and     KONST_1;
+        TB_PCI_IDSEL <= PCI_IDSEL and KONST_1;
+
+        TB_INTAn <= INTAn and KONST_1;
 
-       TB_INTAn                        <=      INTAn                   and     KONST_1;                
-        
-       TB_DEVSELn              <=      DEVSELn when REG_OUT_XX7(7) = '0' else (not REG_OUT_XX7(6));
+        TB_DEVSELn <= DEVSELn when REG_OUT_XX7(7) = '0' else (not REG_OUT_XX7(6));
 
 end architecture MESS_1_TB_DESIGN;