move config space header into pci core directory

[raggedstone] / dhwk / source / verg_8.vhd

diff --git a/dhwk/source/verg_8.vhd b/dhwk/source/verg_8.vhd
index 618a0cca22168df6ac8babd88cfe132c3ac80a55..ea7a499a1746be282560b7a52de5c140e759ff40 100644 (file)
--- a/dhwk/source/verg_8.vhd
+++ b/dhwk/source/verg_8.vhd
@@ -7,22 +7,21 @@ library ieee;
 use ieee.std_logic_1164.all;
 
 entity VERG_8 is
-       port
-       (
-       GLEICH                  :in             std_logic_vector(7 downto 0);
-       GLEICH_OUT      :out    std_logic
-       );
+        port
+        (
+                GLEICH :in std_logic_vector(7 downto 0);
+                GLEICH_OUT :out std_logic
+        );
 
-end entity VERG_8 ;
+end entity VERG_8;
 
 architecture VERG_8_DESIGN of VERG_8 is
- 
 
 begin
 
---     GLEICH(0) nicht noetig. Addr-Bereich = 16 Byte
+ -- GLEICH(0) nicht noetig. Addr-Bereich = 16 Byte
 
---     GLEICH_OUT      <=      '1'     when    GLEICH(7 downto 0)      =       "11111111"      else    '0';    
-               GLEICH_OUT      <=      '1'     when    GLEICH(7 downto 1)      =       "1111111"               else    '0'; 
- 
-end architecture VERG_8_DESIGN ;
+ -- GLEICH_OUT <= '1' when GLEICH(7 downto 0) = "11111111" else '0';
+    GLEICH_OUT <= '1' when GLEICH(7 downto 1) = "1111111" else '0';
+
+end architecture VERG_8_DESIGN;