identing

[raggedstone] / dhwk / source / Parity_4.vhd

diff --git a/dhwk/source/Parity_4.vhd b/dhwk/source/Parity_4.vhd
index 4f06bd623c9203b7d6accd0df6e0508e546fdf3d..0942c2633245582c3096287fa2322711be84b088 100644 (file)
--- a/dhwk/source/Parity_4.vhd
+++ b/dhwk/source/Parity_4.vhd
@@ -7,17 +7,17 @@ library ieee;
 use ieee.std_logic_1164.all;
 
 entity PARITY_4 is
-       port
-       (
-       PAR_IN  :in             std_logic_vector(3 downto 0);   
-       PAR_OUT :out    std_logic
-       );
-end entity PARITY_4 ; 
+        port
+        (
+                PAR_IN :in std_logic_vector(3 downto 0);
+                PAR_OUT :out std_logic
+        );
+end entity PARITY_4;
 
 architecture PARITY_4_DESIGN of PARITY_4 is
 
 begin
 
-       PAR_OUT <= PAR_IN(3) xor PAR_IN(2) xor PAR_IN(1) xor PAR_IN(0) ;
+        PAR_OUT <= PAR_IN(3) xor PAR_IN(2) xor PAR_IN(1) xor PAR_IN(0);
 
 end architecture PARITY_4_DESIGN;