identing

[raggedstone] / dhwk / source / REG.vhd

diff --git a/dhwk/source/REG.vhd b/dhwk/source/REG.vhd
index 10a25a8268f6885cff15c86fd5867be7cd5c25d7..7201b3a8538f968e448e41090da6f368064787f6 100644 (file)
--- a/dhwk/source/REG.vhd
+++ b/dhwk/source/REG.vhd
@@ -3,36 +3,41 @@
 -- 23.08.2006
 -- File: REG.VHD
 
-library ieee ;
-use ieee.std_logic_1164.all ;
+library ieee;
+use ieee.std_logic_1164.all;
 
 entity REG is
-       port
-       (
-       CLOCK           :in             std_logic; 
-       RESET           :in             std_logic; 
-       WRITE           :in             std_logic;   
-       REG_IN  :in             std_logic_vector(7 downto 0);
-       REG_OUT :out    std_logic_vector(7 downto 0) 
-       );
-end entity REG ;
+        port
+        (
+                CLOCK :in std_logic;
+                RESET :in std_logic;
+                WRITE :in std_logic;
+                REG_IN :in std_logic_vector(7 downto 0);
+                REG_OUT :out std_logic_vector(7 downto 0)
+        );
+end entity REG;
 
 architecture REG_DESIGN of REG is
 
-       signal SIG_REG  :std_logic_vector (7 downto 0);
+        signal SIG_REG :std_logic_vector (7 downto 0);
 
 begin
 
-       process (CLOCK) 
-       begin
-               if (CLOCK'event and CLOCK = '1') then
-                       if                      RESET   =       '1'     then    SIG_REG <= X"00";
-                               elsif   WRITE   =       '1'     then    SIG_REG <= REG_IN;
-                               else                                                                            SIG_REG <= SIG_REG;
-               end if;
-               end if;
-       end process;
-
-       REG_OUT <= SIG_REG;
+        process (CLOCK)
+        begin
+                if (CLOCK'event and CLOCK = '1') then
+                        if RESET = '1' then
+                                SIG_REG <= X"00";
+
+                        elsif WRITE = '1' then
+                                SIG_REG <= REG_IN;
+
+                        else
+                                SIG_REG <= SIG_REG;
+                        end if;
+                end if;
+        end process;
+
+        REG_OUT <= SIG_REG;
 
 end architecture REG_DESIGN;