identing

[raggedstone] / dhwk / source / Verg_4.vhd

diff --git a/dhwk/source/Verg_4.vhd b/dhwk/source/Verg_4.vhd
index e3900cf4e2703a75d638ea7fcf679d72332c6155..02edc302327623ed6d5e1f94772cd89a28ea577d 100644 (file)
--- a/dhwk/source/Verg_4.vhd
+++ b/dhwk/source/Verg_4.vhd
@@ -7,26 +7,27 @@ library ieee;
 use ieee.std_logic_1164.all;
 
 entity VERG_4 is
-       port
-       (
-       IN_A            :in             std_logic_vector(3 downto 0);
-       IN_B            :in             std_logic_vector(3 downto 0);
-       GLEICH  :out    std_logic
-       );
-end entity VERG_4 ;
+        port
+        (
+                IN_A :in std_logic_vector(3 downto 0);
+                IN_B :in std_logic_vector(3 downto 0);
+                GLEICH :out std_logic
+        );
+end entity VERG_4;
 
 architecture VERG_4_DESIGN of VERG_4 is
 
 begin
 
-       process (IN_A,IN_B) 
-       begin 
+        process (IN_A,IN_B)
+        begin
 
-               if                      IN_A    =       IN_B    then    GLEICH  <=      '1';
-                       else                                                                                    GLEICH  <=      '0';   
-               end if;
-
-       end process;
+                if IN_A = IN_B then
+                        GLEICH <= '1';
+                else
+                        GLEICH <= '0';
+                end if;
+        end process;
 
 end architecture VERG_4_DESIGN;