- port
- (
- READ_SEL :in std_logic_vector( 1 downto 0);
- ADDR_REG :in std_logic_vector(31 downto 0);
- CBE_REGn :in std_logic_vector( 3 downto 0);
- MUX_IN_XX0 :in std_logic_vector( 7 downto 0);
- MUX_IN_XX1 :in std_logic_vector( 7 downto 0);
- MUX_IN_XX2 :in std_logic_vector( 7 downto 0);
- MUX_IN_XX3 :in std_logic_vector( 7 downto 0);
- MUX_IN_XX4 :in std_logic_vector( 7 downto 0);
- MUX_IN_XX5 :in std_logic_vector( 7 downto 0);
- MUX_IN_XX6 :in std_logic_vector( 7 downto 0);
- MUX_IN_XX7 :in std_logic_vector( 7 downto 0);
- MUX_OUT :out std_logic_vector(31 downto 0);
- READ_XX1_0 :out std_logic;
- READ_XX3_2 :out std_logic;
- READ_XX5_4 :out std_logic;
- READ_XX7_6 :out std_logic
---READ_FIFO :out std_logic
- );
-end entity DATA_MUX ;
+ port
+ (
+ READ_SEL :in std_logic_vector( 1 downto 0);
+ ADDR_REG :in std_logic_vector(31 downto 0);
+ CBE_REGn :in std_logic_vector( 3 downto 0);
+ MUX_IN_XX0 :in std_logic_vector( 7 downto 0);
+ MUX_IN_XX1 :in std_logic_vector( 7 downto 0);
+ MUX_IN_XX2 :in std_logic_vector( 7 downto 0);
+ MUX_IN_XX3 :in std_logic_vector( 7 downto 0);
+ MUX_IN_XX4 :in std_logic_vector( 7 downto 0);
+ MUX_IN_XX5 :in std_logic_vector( 7 downto 0);
+ MUX_IN_XX6 :in std_logic_vector( 7 downto 0);
+ MUX_IN_XX7 :in std_logic_vector( 7 downto 0);
+ MUX_OUT :out std_logic_vector(31 downto 0);
+ READ_XX1_0 :out std_logic;
+ READ_XX3_2 :out std_logic;
+ READ_XX5_4 :out std_logic;
+ READ_XX7_6 :out std_logic
+ --READ_FIFO :out std_logic
+ );
+end entity DATA_MUX;