use IEEE.std_logic_1164.all;
entity CONFIG_10H is
- port
- (
- PCI_CLOCK :in std_logic;
- PCI_RSTn :in std_logic;
- AD_REG :in std_logic_vector(31 downto 0);
- CBE_REGn :in std_logic_vector( 3 downto 0);
- CONF_WR_10H :in std_logic;
- CONF_DATA_10H :out std_logic_vector(31 downto 0)
- );
+ port
+ (
+ PCI_CLOCK :in std_logic;
+ PCI_RSTn :in std_logic;
+ AD_REG :in std_logic_vector(31 downto 0);
+ CBE_REGn :in std_logic_vector( 3 downto 0);
+ CONF_WR_10H :in std_logic;
+ CONF_DATA_10H :out std_logic_vector(31 downto 0)
+ );
end entity CONFIG_10H;
architecture CONFIG_10H_DESIGN of CONFIG_10H is
- signal CONF_BAS_ADDR_REG :std_logic_vector(31 downto 0);
+ signal CONF_BAS_ADDR_REG :std_logic_vector(31 downto 0);
begin
---*******************************************************************
---***** PCI Configuration Space Header "BASE ADDRESS REGISTER" ******
---*******************************************************************
+ --*******************************************************************
+ --***** PCI Configuration Space Header "BASE ADDRESS REGISTER" ******
+ --*******************************************************************
- CONF_BAS_ADDR_REG(1 downto 0) <= "01" ;-- Base Address Register for "I/O"
- CONF_BAS_ADDR_REG(3 downto 2) <= "00" ;-- IO Bereich = 16 BYTE
+ CONF_BAS_ADDR_REG(1 downto 0) <= "01";-- Base Address Register for "I/O"
+ CONF_BAS_ADDR_REG(3 downto 2) <= "00";-- IO Bereich = 16 BYTE
- process (PCI_CLOCK,PCI_RSTn)
- begin
+ process (PCI_CLOCK,PCI_RSTn)
+ begin
--- if PCI_RSTn = '0' then CONF_BAS_ADDR_REG(31 downto 2) <= (others =>'0');
- if PCI_RSTn = '0' then CONF_BAS_ADDR_REG(31 downto 4) <= (others =>'0');
-
- elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then
+ -- if PCI_RSTn = '0' then CONF_BAS_ADDR_REG(31 downto 2) <= (others =>'0');
+ if PCI_RSTn = '0' then
+ CONF_BAS_ADDR_REG(31 downto 4) <= (others =>'0');
- if CONF_WR_10H = '1'and CBE_REGn(3) = '0' then
+ elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then
- CONF_BAS_ADDR_REG(31 downto 24) <= AD_REG(31 downto 24);
+ if CONF_WR_10H = '1'and CBE_REGn(3) = '0' then
+ CONF_BAS_ADDR_REG(31 downto 24) <= AD_REG(31 downto 24);
+ else
+ CONF_BAS_ADDR_REG(31 downto 24) <= CONF_BAS_ADDR_REG(31 downto 24);
+ end if;
- else CONF_BAS_ADDR_REG(31 downto 24) <= CONF_BAS_ADDR_REG(31 downto 24);
- end if;
+ if CONF_WR_10H = '1'and CBE_REGn(2) = '0' then
+ CONF_BAS_ADDR_REG(23 downto 16) <= AD_REG(23 downto 16);
+ else
+ CONF_BAS_ADDR_REG(23 downto 16) <= CONF_BAS_ADDR_REG(23 downto 16);
+ end if;
- if CONF_WR_10H = '1'and CBE_REGn(2) = '0' then
+ if CONF_WR_10H = '1'and CBE_REGn(1) = '0' then
+ CONF_BAS_ADDR_REG(15 downto 8) <= AD_REG(15 downto 8);
+ else
+ CONF_BAS_ADDR_REG(15 downto 8) <= CONF_BAS_ADDR_REG(15 downto 8);
+ end if;
- CONF_BAS_ADDR_REG(23 downto 16) <= AD_REG(23 downto 16);
+ -- if CONF_WR_10H = '1'and CBE_REGn(0) = '0' then
+ -- CONF_BAS_ADDR_REG( 7 downto 2) <= AD_REG( 7 downto 2);
+ -- else
+ -- CONF_BAS_ADDR_REG( 7 downto 2) <= CONF_BAS_ADDR_REG( 7 downto 2);
+ -- end if;
- else CONF_BAS_ADDR_REG(23 downto 16) <= CONF_BAS_ADDR_REG(23 downto 16);
- end if;
+ if CONF_WR_10H = '1'and CBE_REGn(0) = '0' then
+ CONF_BAS_ADDR_REG( 7 downto 4) <= AD_REG( 7 downto 4);
+ else
+ CONF_BAS_ADDR_REG( 7 downto 4) <= CONF_BAS_ADDR_REG( 7 downto 4);
+ end if;
+ end if;
+end process;
- if CONF_WR_10H = '1'and CBE_REGn(1) = '0' then
-
- CONF_BAS_ADDR_REG(15 downto 8) <= AD_REG(15 downto 8);
-
- else CONF_BAS_ADDR_REG(15 downto 8) <= CONF_BAS_ADDR_REG(15 downto 8);
- end if;
-
--- if CONF_WR_10H = '1'and CBE_REGn(0) = '0' then
---
--- CONF_BAS_ADDR_REG( 7 downto 2) <= AD_REG( 7 downto 2);
---
--- else CONF_BAS_ADDR_REG( 7 downto 2) <= CONF_BAS_ADDR_REG( 7 downto 2);
--- end if;
-
- if CONF_WR_10H = '1'and CBE_REGn(0) = '0' then
-
- CONF_BAS_ADDR_REG( 7 downto 4) <= AD_REG( 7 downto 4);
-
- else CONF_BAS_ADDR_REG( 7 downto 4) <= CONF_BAS_ADDR_REG( 7 downto 4);
- end if;
-
-
- end if;
-
- end process;
-
- CONF_DATA_10H <= CONF_BAS_ADDR_REG;
+CONF_DATA_10H <= CONF_BAS_ADDR_REG;
end architecture CONFIG_10H_DESIGN;
-
-
-