- port
- (
- PCI_CLOCK :in std_logic;
- WRITE_XX1_0 :in std_logic; -- PCI Write
- FIFO_RDn :in std_logic; -- FIFO Read (low active)
- RESET :in std_logic;
- SYNC_FLAG_1 :in std_logic; -- Recv FIFO Empty (low active)
- SYNC_FLAG_7 :in std_logic; -- Send FIFO Full (low active)
- S_FIFO_RESETn :out std_logic; -- Send FIFO Reset (low active)
- R_FIFO_RESETn :out std_logic; -- Recv FIFO Reset (low active)
- S_FIFO_WRITEn :out std_logic; -- Send FIFO Write (low active)
- R_FIFO_READn :out std_logic; -- Recv FIFO Read (low active)
- S_FIFO_RETRANSMITn :out std_logic; -- Send FIFO Retransmit (low active)
- R_FIFO_RETRANSMITn :out std_logic; -- Recv FIFO Retransmit (low active)
- S_ERROR :out std_logic; -- Send ERROR
- R_ERROR :out std_logic; -- Recv ERROR
- SR_ERROR :out std_logic -- Send / Recv Error
- );
+ port
+ (
+ PCI_CLOCK :in std_logic;
+ WRITE_XX1_0 :in std_logic; -- PCI Write
+ FIFO_RDn :in std_logic; -- FIFO Read (low active)
+ RESET :in std_logic;
+ SYNC_FLAG_1 :in std_logic; -- Recv FIFO Empty (low active)
+ SYNC_FLAG_7 :in std_logic; -- Send FIFO Full (low active)
+ S_FIFO_RESETn :out std_logic; -- Send FIFO Reset (low active)
+ R_FIFO_RESETn :out std_logic; -- Recv FIFO Reset (low active)
+ S_FIFO_WRITEn :out std_logic; -- Send FIFO Write (low active)
+ R_FIFO_READn :out std_logic; -- Recv FIFO Read (low active)
+ S_FIFO_RETRANSMITn :out std_logic; -- Send FIFO Retransmit (low active)
+ R_FIFO_RETRANSMITn :out std_logic; -- Recv FIFO Retransmit (low active)
+ S_ERROR :out std_logic; -- Send ERROR
+ R_ERROR :out std_logic; -- Recv ERROR
+ SR_ERROR :out std_logic -- Send / Recv Error
+ );
-process (PCI_CLOCK)
-begin
- if (PCI_CLOCK'event and PCI_CLOCK ='1') then
- S_FIFO_RESETn <= not RESET;
- R_FIFO_RESETn <= not RESET;
- end if;
-end process;
+ process (PCI_CLOCK)
+ begin
+ if (PCI_CLOCK'event and PCI_CLOCK ='1') then
+ S_FIFO_RESETn <= not RESET;
+ R_FIFO_RESETn <= not RESET;
+ end if;
+ end process;
-process (PCI_CLOCK)
-begin
- if (PCI_CLOCK'event and PCI_CLOCK ='1') then
- S_FIFO_RETRANSMITn <= '1';
- R_FIFO_RETRANSMITn <= '1';
- end if;
-end process;
-
+ process (PCI_CLOCK)
+ begin
+ if (PCI_CLOCK'event and PCI_CLOCK ='1') then
+ S_FIFO_RETRANSMITn <= '1';
+ R_FIFO_RETRANSMITn <= '1';
+ end if;
+ end process;
+