- SIGNAL gnd : std_logic := '0';
- SIGNAL vcc : std_logic := '1';
-
- signal IO_DATA : std_logic_vector (31 downto 0);
- signal AD_REG_DUMMY : std_logic_vector (31 downto 0);
-
- component ADDRESS_REGISTER
- Port ( AD_REG : In std_logic_vector (31 downto 0);
- LOAD_ADDR_REG : In std_logic;
- PCI_CLOCK : In std_logic;
- PCI_RSTn : In std_logic;
- ADDR_REG : Out std_logic_vector (31 downto 0) );
- end component;
-
- component IO_REG
- Port ( IO_DATA : In std_logic_vector (31 downto 0);
- OE_PCI_AD : In std_logic;
- PCI_CBEn : In std_logic_vector (3 downto 0);
- PCI_CLOCK : In std_logic;
- PCI_FRAMEn : In std_logic;
- PCI_IDSEL : In std_logic;
- PCI_IRDYn : In std_logic;
- PCI_PAR : In std_logic;
- PCI_RSTn : In std_logic;
- AD_REG : Out std_logic_vector (31 downto 0);
- CBE_REGn : Out std_logic_vector (3 downto 0);
- FRAME_REGn : Out std_logic;
- IDSEL_REG : Out std_logic;
- IRDY_REGn : Out std_logic;
- PAR_REG : Out std_logic;
- PCI_AD : Out std_logic_vector (31 downto 0) );
- end component;
-
- component IO_MUX
- Port ( CONFIG_DATA : In std_logic_vector (31 downto 0);
- PCI_AD : In std_logic_vector (31 downto 0);
- READ_SEL : In std_logic_vector (1 downto 0);
- USER_DATA : In std_logic_vector (31 downto 0);
- IO_DATA : Out std_logic_vector (31 downto 0) );
- end component;
+ SIGNAL gnd : std_logic := '0';
+ SIGNAL vcc : std_logic := '1';
+
+ signal IO_DATA : std_logic_vector (31 downto 0);
+ signal AD_REG_DUMMY : std_logic_vector (31 downto 0);
+
+ component ADDRESS_REGISTER
+ Port ( AD_REG : In std_logic_vector (31 downto 0);
+ LOAD_ADDR_REG : In std_logic;
+ PCI_CLOCK : In std_logic;
+ PCI_RSTn : In std_logic;
+ ADDR_REG : Out std_logic_vector (31 downto 0) );
+ end component;
+
+ component IO_REG
+ Port ( IO_DATA : In std_logic_vector (31 downto 0);
+ OE_PCI_AD : In std_logic;
+ PCI_CBEn : In std_logic_vector (3 downto 0);
+ PCI_CLOCK : In std_logic;
+ PCI_FRAMEn : In std_logic;
+ PCI_IDSEL : In std_logic;
+ PCI_IRDYn : In std_logic;
+ PCI_PAR : In std_logic;
+ PCI_RSTn : In std_logic;
+ AD_REG : Out std_logic_vector (31 downto 0);
+ CBE_REGn : Out std_logic_vector (3 downto 0);
+ FRAME_REGn : Out std_logic;
+ IDSEL_REG : Out std_logic;
+ IRDY_REGn : Out std_logic;
+ PAR_REG : Out std_logic;
+ PCI_AD : Out std_logic_vector (31 downto 0) );
+ end component;
+
+ component IO_MUX
+ Port ( CONFIG_DATA : In std_logic_vector (31 downto 0);
+ PCI_AD : In std_logic_vector (31 downto 0);
+ READ_SEL : In std_logic_vector (1 downto 0);
+ USER_DATA : In std_logic_vector (31 downto 0);
+ IO_DATA : Out std_logic_vector (31 downto 0) );
+ end component;