update to EDK 9.1i

[raggedstone] / dhwk_old / source / wb_fifo.v

diff --git a/dhwk_old/source/wb_fifo.v b/dhwk_old/source/wb_fifo.v
index 5f56b648db4e75f326e303a573f99e099b4a53ed..8605504e684992f39238927b0f21bed6063639e5 100644 (file)
--- a/dhwk_old/source/wb_fifo.v
+++ b/dhwk_old/source/wb_fifo.v
@@ -1,4 +1,4 @@
-module wb_7seg_new (clk_i, nrst_i, wb_adr_i, wb_dat_o, wb_dat_i, wb_sel_i, wb_we_i, \r
+module wb_fifo (clk_i, nrst_i, wb_adr_i, wb_dat_o, wb_dat_i, wb_sel_i, wb_we_i, \r
        wb_stb_i, wb_cyc_i, wb_ack_o, wb_err_o, wb_int_o, fifo_data_i, fifo_data_o, fifo_we_o, fifo_re_o);\r
 \r
        input clk_i;\r
@@ -18,17 +18,20 @@ module wb_7seg_new (clk_i, nrst_i, wb_adr_i, wb_dat_o, wb_dat_i, wb_sel_i, wb_we
         output fifo_we_o;\r
         output fifo_re_o;\r
 \r
-       reg [15:0]      data_reg;\r
+       reg [15:0] data_reg;\r
 \r
        always @(posedge clk_i or negedge nrst_i)\r
        begin\r
                if (nrst_i == 0)\r
-                       data_reg <= 16'hABCD;\r
+                       data_reg <= 16'h0000;\r
                else \r
-                       if (wb_stb_i && wb_we_i)\r
-                               data_reg <= wb_dat_i;\r
+                        if (wb_stb_i && wb_we_i)\r
+                                data_reg <= wb_dat_i;\r
        end\r
 \r
+        assign fifo_we_o = 1'b1;\r
+        assign fifo_data_o = data_reg;\r
+\r
        assign wb_ack_o = wb_stb_i;\r
        assign wb_err_o = 1'b0;\r
        assign wb_int_o = 1'b0;\r