a bit better

[raggedstone] / ethernet / source / top.vhd

diff --git a/ethernet/source/top.vhd b/ethernet/source/top.vhd
index 611e9c0bb707ee025541762637d4367eb22e81ab..1617eee849ab9d826f2c772d6e921d5bd7122aae 100644 (file)
--- a/ethernet/source/top.vhd
+++ b/ethernet/source/top.vhd
@@ -171,6 +171,14 @@ port (
        );
 end component;
 
+component phydcm is
+port ( CLKIN_IN        : in    std_logic;
+       RST_IN          : in    std_logic;
+       CLKFX_OUT       : out   std_logic;
+       CLK0_OUT        : out   std_logic;
+       LOCKED_OUT      : out   std_logic);
+end component;
+
 signal pci_rst_o : std_logic;
 signal pci_rst_oe_o : std_logic;
 signal pci_inta_o : std_logic;
@@ -258,7 +266,6 @@ wb_adr_i(11 downto 8) <= (others => '0');
 wb_adr_i(7 downto 2)  <= wbm_adr_o (7 downto 2);
 
 wb_clk_i <= PCI_CLOCK;
-PHY_CLOCK <= PCI_CLOCK;
 
 data(31 downto 0)  <= wbm_adr_o;
 data(40 downto 33) <= wbm_adr_o (7 downto 0);
@@ -394,4 +401,13 @@ port map (
        trig0 => trig0
        );
 
+eth_dcm : phydcm
+port map (
+       CLKIN_IN => PCI_CLOCK,
+       RST_IN => not PCI_RSTn,
+       CLKFX_OUT => PHY_CLOCK,
+       CLK0_OUT => open,
+       LOCKED_OUT => open
+       );
+
 end architecture ethernet_arch;