clock

[raggedstone] / ethernet / source / top.vhd

diff --git a/ethernet/source/top.vhd b/ethernet/source/top.vhd
index c031ae6f46540bd42c64d38f678e0f91e900030b..611e9c0bb707ee025541762637d4367eb22e81ab 100644 (file)
--- a/ethernet/source/top.vhd
+++ b/ethernet/source/top.vhd
@@ -32,6 +32,8 @@ PORT(
         MD_PAD_IO : INOUT std_logic;
         MDC_PAD_O : OUT std_logic;
 
+       PHY_CLOCK : OUT std_logic;
+
        LED_2 : OUT std_logic
 );
 end ethernet;
@@ -256,6 +258,7 @@ wb_adr_i(11 downto 8) <= (others => '0');
 wb_adr_i(7 downto 2)  <= wbm_adr_o (7 downto 2);
 
 wb_clk_i <= PCI_CLOCK;
+PHY_CLOCK <= PCI_CLOCK;
 
 data(31 downto 0)  <= wbm_adr_o;
 data(40 downto 33) <= wbm_adr_o (7 downto 0);