// these two defines allow user to select active high or low output enables on PCI bus signals, depending on
// output buffers instantiated. Xilinx FPGAs use active low output enables.
-// `define ACTIVE_LOW_OE
-`define ACTIVE_HIGH_OE
+`define ACTIVE_LOW_OE
+//`define ACTIVE_HIGH_OE
// HOST/GUEST implementation selection - see design document and specification for description of each implementation
// only one can be defined at same time