use internal clock

[raggedstone] / heartbeat / source / top_raggedstone.vhd

diff --git a/heartbeat/source/top_raggedstone.vhd b/heartbeat/source/top_raggedstone.vhd
index 3d369cf5dae28104afb9dd4d3cf51a7dc1c2cd01..01dc26bde0fa09934f30768c7fa92d81b809dbfb 100644 (file)
--- a/heartbeat/source/top_raggedstone.vhd
+++ b/heartbeat/source/top_raggedstone.vhd
@@ -64,11 +64,11 @@ port (
        LED3    : out std_logic;\r
        LED2    : out std_logic;\r
        LED4            : out std_logic;\r
-       LED5            : out std_logic;\r
-       IDE1    : out std_logic;\r
-       IDE2    : out std_logic;\r
-       IDE3    : out std_logic;\r
-       IDE4    : out std_logic\r
+       LED5            : out std_logic\r
+--     IDE1    : out std_logic;\r
+--     IDE2    : out std_logic;\r
+--     IDE3    : out std_logic;\r
+--     IDE4    : out std_logic\r
 \r
 );\r
 end raggedstone;\r
@@ -209,11 +209,11 @@ port map(
        led2_o => LED2,\r
        led3_o => LED3,\r
        led4_o => LED4,\r
-       led5_o => LED5,\r
-       led6_o => IDE1,\r
-       led7_o => IDE2,\r
-       led8_o => IDE3,\r
-       led9_o => IDE4\r
+       led5_o => LED5\r
+--     led6_o => IDE1,\r
+--     led7_o => IDE2,\r
+--     led8_o => IDE3,\r
+--     led9_o => IDE4\r
 );\r
 \r
 end raggedstone_arch;\r