add sources for ide daughterboard cpld

[raggedstone] / dhwk_old / source / generic_fifo_sc_a.v

diff --git a/dhwk_old/source/generic_fifo_sc_a.v b/dhwk_old/source/generic_fifo_sc_a.v
index a04727fe931d9bee0bc09ae7ff015eb2f126cb24..53eb6c5b605e2bc62b0ac8e64356816370e90075 100644 (file)
--- a/dhwk_old/source/generic_fifo_sc_a.v
+++ b/dhwk_old/source/generic_fifo_sc_a.v
@@ -38,17 +38,20 @@
 
 //  CVS Log
 //
-//  $Id: generic_fifo_sc_a.v,v 1.1 2007-02-11 21:58:30 sithglan Exp $
+//  $Id: generic_fifo_sc_a.v,v 1.2 2007-02-11 22:21:28 michael Exp $
 //
-//  $Date: 2007-02-11 21:58:30 $
-//  $Revision: 1.1 $
-//  $Author: sithglan $
+//  $Date: 2007-02-11 22:21:28 $
+//  $Revision: 1.2 $
+//  $Author: michael $
 //  $Locker:  $
 //  $State: Exp $
 //
 // Change History:
 //               $Log: generic_fifo_sc_a.v,v $
-//               Revision 1.1  2007-02-11 21:58:30  sithglan
+//               Revision 1.2  2007-02-11 22:21:28  michael
+//               fix address width
+//
+//               Revision 1.1  2007/02/11 21:58:30  sithglan
 //               += fifo
 //
 //               Revision 1.1.1.1  2002/09/25 05:42:06  rudi
@@ -153,7 +156,7 @@ module generic_fifo_sc_a(clk, rst, clr, din, we, dout, re,
                        level);
 
 parameter dw=8;
-parameter aw=8;
+parameter aw=12;
 parameter n=32;
 parameter max_size = 1<<aw;