more merging
[raggedstone] / dhwk / source / pci / config_space_header.vhd
index ca437c08b769237c7406b6166d39849ba95629dc..0b9817497f50f4c0776b079ab276699baef096d6 100644 (file)
@@ -41,6 +41,80 @@ architecture SCHEMATIC of CONFIG_SPACE_HEADER is
         signal CONF_STATUS :std_logic_vector(31 downto 16);
         signal CONF_COMMAND :std_logic_vector(15 downto 0);
 
+        -- PCI Configuration Space Header
+        --
+        -- \ Bit
+        -- \
+        --Address |31 24|23 16|15 8|7 0|
+        -----------------------------------------------------------------
+        --00 |Device ID |Vendor ID |
+        --04 |Status |Command |
+        --08 |Class Code |Revision ID |
+        --0C |BIST |Header Type |Latency T. |Cache L.S. |
+        --10-24 |Base Address Register |
+        --28 |Cardbus CIS Pointer |
+        --2C |Subsystem ID |Subsystem Vendor ID |
+        --30 |Expansion ROM Base Address |
+        --34 |Reserved |
+        --38 |Reserved |
+        --3C |Max_Lat |Min_Gnt |Int_Pin |Int_Line |
+        --40-FF | |
+        -----------------------------------------------------------------
+
+
+        --PCI Bus Commands
+        --C/BE[3..0] Command Type
+        --------------------------------------
+        -- 0000 Interrupt Acknowledge
+        -- 0001 Special Cycle
+        -- 0010 I/O Read
+        -- 0011 I/O Write
+        -- 0100 Reserved
+        -- 0101 Reserved
+        -- 0110 Memory Read
+        -- 0111 Memory Write
+        --
+        -- 1000 Reserved
+        -- 1001 Reserved
+        -- 1010 Configuration Read
+        -- 1011 Configuration Write
+        -- 1100 Memory Read Multiple
+        -- 1101 Dual Address Cycle
+        -- 1110 Memory Read Line
+        -- 1111 Memory Write and Invalidate
+
+
+        --PCI Byte Enable
+        --C/BE[3..0] gueltige Datenbits
+        -------------------------------
+        -- 0000 AD 31..0
+        -- 1000 AD 23..0
+        -- 1100 AD 15..0
+        -- 1110 AD 7..0
+
+        constant CMD_INT_ACK :std_logic_vector(3 downto 0) := "0000";
+        constant CMD_SP_CYC :std_logic_vector(3 downto 0) := "0001";
+        constant CMD_IO_READ :std_logic_vector(3 downto 0) := "0010";
+        constant CMD_IO_WRITE :std_logic_vector(3 downto 0) := "0011";
+        constant CMD_RES_4 :std_logic_vector(3 downto 0) := "0100";
+        constant CMD_RES_5 :std_logic_vector(3 downto 0) := "0101";
+        constant CMD_MEM_READ :std_logic_vector(3 downto 0) := "0110";
+        constant CMD_MEM_WRITE :std_logic_vector(3 downto 0) := "0111";
+        constant CMD_RES_8 :std_logic_vector(3 downto 0) := "1000";
+        constant CMD_RES_9 :std_logic_vector(3 downto 0) := "1001";
+        constant CMD_CONF_READ :std_logic_vector(3 downto 0) := "1010";
+        constant CMD_CONF_WRITE :std_logic_vector(3 downto 0) := "1011";
+        constant CMD_MEM_READ_M :std_logic_vector(3 downto 0) := "1100";
+        constant CMD_DU_ADR_CYC :std_logic_vector(3 downto 0) := "1101";
+        constant CMD_MEN_READ_L :std_logic_vector(3 downto 0) := "1110";
+        constant CMD_MEM_WRITE_I :std_logic_vector(3 downto 0) := "1111";
+
+        signal CONFIG_ADDR :std_logic_vector(7 downto 0);
+        signal CONFIG_WRITE :std_logic_vector(3 downto 0);
+
+        ----
+        ----
+
         SIGNAL gnd : std_logic := '0';
         SIGNAL vcc : std_logic := '1';
 
@@ -59,16 +133,6 @@ architecture SCHEMATIC of CONFIG_SPACE_HEADER is
                        READ_SEL : Out std_logic_vector (2 downto 0) );
         end component;
 
-        component CONFIG_WR_0
-                Port ( ADDR_REG : In std_logic_vector (31 downto 0);
-                       CF_WR_COM : In std_logic;
-                       IRDY_REGn : In std_logic;
-                       TRDYn : In std_logic;
-                       CONF_WR_04H : Out std_logic;
-                       CONF_WR_10H : Out std_logic;
-                       CONF_WR_3CH : Out std_logic );
-        end component;
-
 begin
         CONF_DATA_00H <= CONF_DEVICE_ID & VENDOR_ID;
         CONF_DATA_08H <= CONF_CLASS_CODE & REVISION_ID;
@@ -92,11 +156,6 @@ begin
         Port Map ( ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),
                    CF_RD_COM=>CF_RD_COM,
                    READ_SEL(2 downto 0)=>CONF_READ_SEL(2 downto 0) );
-        I8 : CONFIG_WR_0
-        Port Map ( ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),
-                   CF_WR_COM=>CF_WR_COM, IRDY_REGn=>IRDY_REGn,
-                   TRDYn=>TRDYn, CONF_WR_04H=>CONF_WR_04H,
-                   CONF_WR_10H=>CONF_WR_10H, CONF_WR_3CH=>CONF_WR_3CH );
 
         process (PCI_CLOCK,PCI_RSTn)
         begin
@@ -231,4 +290,42 @@ begin
                         end if;
                 end if;
         end process;
+
+
+        --*******************************************************************
+        --******************* PCI Write Configuration Address ***************
+        --*******************************************************************
+
+        CONFIG_ADDR(7 downto 0) <= ADDR_REG(7 downto 0);
+
+
+        process (CF_WR_COM,IRDY_REGn,TRDYn,CONFIG_ADDR)
+        begin
+
+                if CF_WR_COM = '1' and IRDY_REGn = '0' and TRDYn = '0' then
+
+                        if CONFIG_ADDR = X"04" then
+                                CONFIG_WRITE <= "0001";
+
+                        elsif CONFIG_ADDR = X"10" then
+                                CONFIG_WRITE <= "0010";
+
+                        elsif CONFIG_ADDR = X"3C" then
+                                CONFIG_WRITE <= "0100";
+
+                        -- elsif CONFIG_ADDR = X"40" then
+                        --         CONFIG_WRITE <= "1000";
+                        else
+                                CONFIG_WRITE <= "0000";
+                        end if;
+                else
+                        CONFIG_WRITE <= "0000";
+                end if;
+        end process;
+
+        CONF_WR_04H <= CONFIG_WRITE(0);
+        CONF_WR_10H <= CONFIG_WRITE(1);
+        CONF_WR_3CH <= CONFIG_WRITE(2);
+        --CONF_WR_40H <= CONFIG_WRITE(3);
+
 end SCHEMATIC;
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