rename fifo to dhwk_fifo

[raggedstone] / dhwk / source / top.vhd

diff --git a/dhwk/source/top.vhd b/dhwk/source/top.vhd
index e2f307c0e6266ff027978c13b07d9ba352ff5594..bf927d84931e93850197a826d2207a781a7f31c1 100644 (file)
--- a/dhwk/source/top.vhd
+++ b/dhwk/source/top.vhd
@@ -92,8 +92,8 @@ architecture SCHEMATIC of dhwk is
    signal SPC_RDY_OUT : std_logic;\r
    signal watch : std_logic;\r
    signal control0       : std_logic_vector(35 downto 0);\r
-   signal data       : std_logic_vector(35 downto 0);\r
-   signal trig0      : std_logic_vector(7 downto 0);\r
+   signal data       : std_logic_vector(95 downto 0);\r
+   signal trig0      : std_logic_vector(31 downto 0);\r
 \r
    component MESS_1_TB\r
       Port ( DEVSELn : In    std_logic;\r
@@ -169,7 +169,6 @@ architecture SCHEMATIC of dhwk is
              SERIAL_OUT : Out   std_logic;\r
              SPC_RDY_OUT : Out   std_logic;\r
              SR_ERROR : Out   std_logic;\r
-            PAR_SER_IN : Out std_logic_vector (7 downto 0);\r
              SYNC_FLAG : Out   std_logic_vector (7 downto 0) );\r
    end component;\r
 \r
@@ -210,7 +209,7 @@ architecture SCHEMATIC of dhwk is
              WRITE_XX7_6 : Out   std_logic );\r
    end component;\r
 \r
-component fifo_generator_v3_2\r
+component dhwk_fifo\r
         port (\r
         clk: IN std_logic;\r
         din: IN std_logic_VECTOR(7 downto 0);\r
@@ -237,8 +236,8 @@ end component;
     (\r
       control     : in    std_logic_vector(35 downto 0);\r
       clk         : in    std_logic;\r
-      data        : in    std_logic_vector(35 downto 0);\r
-      trig0       : in    std_logic_vector(7 downto 0)\r
+      data        : in    std_logic_vector(95 downto 0);\r
+      trig0       : in    std_logic_vector(31 downto 0)\r
     );\r
   end component;\r
 \r
@@ -251,9 +250,28 @@ begin
        LED_4 <= '0';\r
        LED_5 <= not watch;\r
        PCI_INTAn <= watch;\r
-       trig0(7 downto 0) <= (0 => watch, others => '0');\r
+       trig0(31 downto 0) <= (\r
+               0 => watch,\r
+               1 => R_FIFO_READn,\r
+               2 => R_FIFO_WRITEn,\r
+               3 => S_FIFO_READn,\r
+               4 => S_FIFO_WRITEn, \r
+               16 => PCI_AD(0),\r
+               17 => PCI_AD(1),\r
+               18 => PCI_AD(2),\r
+               19 => PCI_AD(3),\r
+               20 => PCI_AD(4),\r
+               21 => PCI_AD(5),\r
+               22 => PCI_AD(6),\r
+               23 => PCI_AD(7),\r
+               27 => PCI_FRAMEn,\r
+               28 => PCI_CBEn(0),\r
+               29 => PCI_CBEn(1),\r
+               30 => PCI_CBEn(2),\r
+               31 => PCI_CBEn(3),\r
+               others => '0');\r
+\r
        data(0) <= watch;\r
-       \r
        data(1) <= R_EFn;\r
        data(2) <= R_HFn;\r
        data(3) <= R_FFn;\r
@@ -272,6 +290,11 @@ begin
        data(16) <= SPC_RDY_IN;\r
        data(17) <= SERIAL_OUT;\r
        data(18) <= SPC_RDY_OUT;\r
+       data(26 downto 19) <= S_FIFO_Q_OUT;\r
+       data(34 downto 27) <= R_FIFO_Q_OUT;\r
+       data(66 downto 35) <= PCI_AD(31 downto 0);\r
+       data(70 downto 67) <= PCI_CBEn(3 downto 0);\r
+       data(71) <= PCI_FRAMEn;\r
 \r
    I19 : MESS_1_TB\r
       Port Map ( DEVSELn=>DEVSELn, INTAn=>INTAn, KONST_1=>KONST_1,\r
@@ -313,7 +336,6 @@ begin
                  S_FIFO_RETRANSMITn=>S_FIFO_RTn,\r
                  S_FIFO_WRITEn=>S_FIFO_WRITEn, SERIAL_OUT=>SERIAL_OUT,\r
                  SPC_RDY_OUT=>SPC_RDY_OUT, SR_ERROR=>SR_ERROR,\r
-                PAR_SER_IN(7 downto 0)=>data(26 downto 19),\r
                  SYNC_FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0) );\r
    I1 : PCI_TOP\r
       Port Map ( FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0),\r
@@ -342,7 +364,7 @@ begin
                  WRITE_XX3_2=>WRITE_XX3_2, WRITE_XX5_4=>WRITE_XX5_4,\r
                  WRITE_XX7_6=>WRITE_XX7_6 );\r
 \r
-receive_fifo : fifo_generator_v3_2\r
+receive_fifo : dhwk_fifo\r
                 port map (\r
                         clk => PCI_CLOCK,\r
                         din => R_FIFO_D_IN,\r
@@ -354,7 +376,7 @@ receive_fifo : fifo_generator_v3_2
                         full => R_FFn,\r
                         prog_full => R_HFn);\r
 \r
-send_fifo : fifo_generator_v3_2\r
+send_fifo : dhwk_fifo\r
                 port map (\r
                         clk => PCI_CLOCK,\r
                         din => S_FIFO_D_IN,\r