CBEn

[raggedstone] / dhwk / source / top.vhd

diff --git a/dhwk/source/top.vhd b/dhwk/source/top.vhd
index e2f307c0e6266ff027978c13b07d9ba352ff5594..971b0c49c2104a6b98022a6ff57f6a4cfca2cff5 100644 (file)
--- a/dhwk/source/top.vhd
+++ b/dhwk/source/top.vhd
@@ -92,8 +92,8 @@ architecture SCHEMATIC of dhwk is
    signal SPC_RDY_OUT : std_logic;\r
    signal watch : std_logic;\r
    signal control0       : std_logic_vector(35 downto 0);\r
    signal SPC_RDY_OUT : std_logic;\r
    signal watch : std_logic;\r
    signal control0       : std_logic_vector(35 downto 0);\r

-   signal data       : std_logic_vector(35 downto 0);\r
-   signal trig0      : std_logic_vector(7 downto 0);\r
+   signal data       : std_logic_vector(95 downto 0);\r
+   signal trig0      : std_logic_vector(31 downto 0);\r

 \r
    component MESS_1_TB\r
       Port ( DEVSELn : In    std_logic;\r
 \r
    component MESS_1_TB\r
       Port ( DEVSELn : In    std_logic;\r


@@ -169,7 +169,6 @@ architecture SCHEMATIC of dhwk is
              SERIAL_OUT : Out   std_logic;\r
              SPC_RDY_OUT : Out   std_logic;\r
              SR_ERROR : Out   std_logic;\r
              SERIAL_OUT : Out   std_logic;\r
              SPC_RDY_OUT : Out   std_logic;\r
              SR_ERROR : Out   std_logic;\r

-            PAR_SER_IN : Out std_logic_vector (7 downto 0);\r

              SYNC_FLAG : Out   std_logic_vector (7 downto 0) );\r
    end component;\r
 \r
              SYNC_FLAG : Out   std_logic_vector (7 downto 0) );\r
    end component;\r
 \r


@@ -237,8 +236,8 @@ end component;
     (\r
       control     : in    std_logic_vector(35 downto 0);\r
       clk         : in    std_logic;\r
     (\r
       control     : in    std_logic_vector(35 downto 0);\r
       clk         : in    std_logic;\r

-      data        : in    std_logic_vector(35 downto 0);\r
-      trig0       : in    std_logic_vector(7 downto 0)\r
+      data        : in    std_logic_vector(95 downto 0);\r
+      trig0       : in    std_logic_vector(31 downto 0)\r

     );\r
   end component;\r
 \r
     );\r
   end component;\r
 \r


@@ -251,7 +250,7 @@ begin
        LED_4 <= '0';\r
        LED_5 <= not watch;\r
        PCI_INTAn <= watch;\r
        LED_4 <= '0';\r
        LED_5 <= not watch;\r
        PCI_INTAn <= watch;\r

-       trig0(7 downto 0) <= (0 => watch, others => '0');\r
+       trig0(31 downto 0) <= (0 => watch, 1 => R_FIFO_READn, 2 => R_FIFO_WRITEn, 3 => S_FIFO_READn, 4 => S_FIFO_WRITEn, others => '0');\r

        data(0) <= watch;\r
        \r
        data(1) <= R_EFn;\r
        data(0) <= watch;\r
        \r
        data(1) <= R_EFn;\r


@@ -272,6 +271,10 @@ begin
        data(16) <= SPC_RDY_IN;\r
        data(17) <= SERIAL_OUT;\r
        data(18) <= SPC_RDY_OUT;\r
        data(16) <= SPC_RDY_IN;\r
        data(17) <= SERIAL_OUT;\r
        data(18) <= SPC_RDY_OUT;\r

+       data(26 downto 19) <= S_FIFO_Q_OUT;\r
+       data(34 downto 27) <= R_FIFO_Q_OUT;\r
+       data(66 downto 35) <= PCI_AD(31 downto 0);\r
+       data(70 downto 67) <= PCI_CBEn(3 downto 0);\r

 \r
    I19 : MESS_1_TB\r
       Port Map ( DEVSELn=>DEVSELn, INTAn=>INTAn, KONST_1=>KONST_1,\r
 \r
    I19 : MESS_1_TB\r
       Port Map ( DEVSELn=>DEVSELn, INTAn=>INTAn, KONST_1=>KONST_1,\r


@@ -313,7 +316,6 @@ begin
                  S_FIFO_RETRANSMITn=>S_FIFO_RTn,\r
                  S_FIFO_WRITEn=>S_FIFO_WRITEn, SERIAL_OUT=>SERIAL_OUT,\r
                  SPC_RDY_OUT=>SPC_RDY_OUT, SR_ERROR=>SR_ERROR,\r
                  S_FIFO_RETRANSMITn=>S_FIFO_RTn,\r
                  S_FIFO_WRITEn=>S_FIFO_WRITEn, SERIAL_OUT=>SERIAL_OUT,\r
                  SPC_RDY_OUT=>SPC_RDY_OUT, SR_ERROR=>SR_ERROR,\r

-                PAR_SER_IN(7 downto 0)=>data(26 downto 19),\r

                  SYNC_FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0) );\r
    I1 : PCI_TOP\r
       Port Map ( FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0),\r
                  SYNC_FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0) );\r
    I1 : PCI_TOP\r
       Port Map ( FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0),\r