update to EDK 9.1i

[raggedstone] / ethernet / source / phydcm.vhd

diff --git a/ethernet/source/phydcm.vhd b/ethernet/source/phydcm.vhd
index efec74a17565f26aed7584b0cab3496ba9379185..a5db448e54f5889352f3352705c2a6953f0ca299 100644 (file)
--- a/ethernet/source/phydcm.vhd
+++ b/ethernet/source/phydcm.vhd
@@ -7,7 +7,7 @@
 -- \   \   \/     Version : 9.1.02i
 --  \   \         Application : xaw2vhdl
 --  /   /         Filename : phydcm.vhd
 -- \   \   \/     Version : 9.1.02i
 --  \   \         Application : xaw2vhdl
 --  /   /         Filename : phydcm.vhd

--- /___/   /\     Timestamp : 03/21/2007 14:47:39
+-- /___/   /\     Timestamp : 03/21/2007 14:56:33

 -- \   \  /  \ 
 --  \___\/\___\ 
 --
 -- \   \  /  \ 
 --  \___\/\___\ 
 --


@@ -26,30 +26,23 @@ library UNISIM;
 use UNISIM.Vcomponents.ALL;
 
 entity phydcm is
 use UNISIM.Vcomponents.ALL;
 
 entity phydcm is

-   port ( CLKIN_IN        : in    std_logic; 
-          RST_IN          : in    std_logic; 
-          CLKFX_OUT       : out   std_logic; 
-          CLKIN_IBUFG_OUT : out   std_logic; 
-          CLK0_OUT        : out   std_logic; 
-          LOCKED_OUT      : out   std_logic);
+   port ( CLKIN_IN   : in    std_logic; 
+          RST_IN     : in    std_logic; 
+          CLKFX_OUT  : out   std_logic; 
+          CLK0_OUT   : out   std_logic; 
+          LOCKED_OUT : out   std_logic);

 end phydcm;
 
 architecture BEHAVIORAL of phydcm is
 end phydcm;
 
 architecture BEHAVIORAL of phydcm is

-   signal CLKFB_IN        : std_logic;
-   signal CLKFX_BUF       : std_logic;
-   signal CLKIN_IBUFG     : std_logic;
-   signal CLK0_BUF        : std_logic;
-   signal GND_BIT         : std_logic;
+   signal CLKFB_IN   : std_logic;
+   signal CLKFX_BUF  : std_logic;
+   signal CLK0_BUF   : std_logic;
+   signal GND_BIT    : std_logic;

    component BUFG
       port ( I : in    std_logic; 
              O : out   std_logic);
    end component;
    
    component BUFG
       port ( I : in    std_logic; 
              O : out   std_logic);
    end component;
    

-   component IBUFG
-      port ( I : in    std_logic; 
-             O : out   std_logic);
-   end component;
-   

    -- Period Jitter (unit interval) for block DCM_INST = 0.06 UI
    -- Period Jitter (Peak-to-Peak) for block DCM_INST = 2.27 ns
    component DCM
    -- Period Jitter (unit interval) for block DCM_INST = 0.06 UI
    -- Period Jitter (Peak-to-Peak) for block DCM_INST = 2.27 ns
    component DCM


@@ -91,16 +84,11 @@ architecture BEHAVIORAL of phydcm is
    
 begin
    GND_BIT <= '0';
    
 begin
    GND_BIT <= '0';

-   CLKIN_IBUFG_OUT <= CLKIN_IBUFG;

    CLK0_OUT <= CLKFB_IN;
    CLKFX_BUFG_INST : BUFG
       port map (I=>CLKFX_BUF,
                 O=>CLKFX_OUT);
    
    CLK0_OUT <= CLKFB_IN;
    CLKFX_BUFG_INST : BUFG
       port map (I=>CLKFX_BUF,
                 O=>CLKFX_OUT);
    

-   CLKIN_IBUFG_INST : IBUFG
-      port map (I=>CLKIN_IN,
-                O=>CLKIN_IBUFG);
-   

    CLK0_BUFG_INST : BUFG
       port map (I=>CLK0_BUF,
                 O=>CLKFB_IN);
    CLK0_BUFG_INST : BUFG
       port map (I=>CLK0_BUF,
                 O=>CLKFB_IN);


@@ -121,7 +109,7 @@ begin
             PHASE_SHIFT => 0,
             STARTUP_WAIT => FALSE)
       port map (CLKFB=>CLKFB_IN,
             PHASE_SHIFT => 0,
             STARTUP_WAIT => FALSE)
       port map (CLKFB=>CLKFB_IN,

-                CLKIN=>CLKIN_IBUFG,
+                CLKIN=>CLKIN_IN,

                 DSSEN=>GND_BIT,
                 PSCLK=>GND_BIT,
                 PSEN=>GND_BIT,
                 DSSEN=>GND_BIT,
                 PSCLK=>GND_BIT,
                 PSEN=>GND_BIT,