--- /dev/null
+--+-------------------------------------------------------------------------------------------------+\r
+--| |\r
+--| File: top.vhd |\r
+--| |\r
+--| Components: pci32lite.vhd |\r
+--| pciwbsequ.vhd |\r
+--| pcidmux.vhd |\r
+--| pciregs.vhd |\r
+--| pcipargen.vhd |\r
+--| -- Libs -- |\r
+--| ona.vhd |\r
+--| |\r
+--| Description: RS1 PCI Demo : (TOP) Main file. |\r
+--| |\r
+--| |\r
+--| |\r
+--+-------------------------------------------------------------------------------------------------+\r
+--| |\r
+--| Revision history : |\r
+--| Date Version Author Description |\r
+--| |\r
+--| |\r
+--| To do: |\r
+--| |\r
+--+-------------------------------------------------------------------------------------------------+\r
+\r
+\r
+--+-----------------------------------------------------------------------------+\r
+--| LIBRARIES |\r
+--+-----------------------------------------------------------------------------+\r
+\r
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.std_logic_arith.all;\r
+use ieee.std_logic_unsigned.all;\r
+\r
+--+-----------------------------------------------------------------------------+\r
+--| ENTITY |\r
+--+-----------------------------------------------------------------------------+\r
+\r
+entity dhwk is\r
+port (\r
+\r
+ -- General \r
+ PCI_CLK : in std_logic;\r
+ PCI_nRES : in std_logic;\r
+ \r
+ -- PCI target 32bits\r
+ PCI_AD : inout std_logic_vector(31 downto 0);\r
+ PCI_CBE : in std_logic_vector(3 downto 0);\r
+ PCI_PAR : out std_logic; \r
+ PCI_nFRAME : in std_logic;\r
+ PCI_nIRDY : in std_logic;\r
+ PCI_nTRDY : out std_logic;\r
+ PCI_nDEVSEL : out std_logic;\r
+ PCI_nSTOP : out std_logic;\r
+ PCI_IDSEL : in std_logic;\r
+ PCI_nPERR : out std_logic;\r
+ PCI_nSERR : out std_logic;\r
+ PCI_nINT : out std_logic;\r
+ \r
+ -- debug signals\r
+ LED3 : out std_logic;\r
+ LED2 : out std_logic;\r
+ LED4 : out std_logic;\r
+ LED5 : out std_logic\r
+\r
+);\r
+end dhwk;\r
+\r
+\r
+--+-----------------------------------------------------------------------------+\r
+--| ARCHITECTURE |\r
+--+-----------------------------------------------------------------------------+\r
+\r
+architecture dhwk_arch of dhwk is\r
+\r
+\r
+--+-----------------------------------------------------------------------------+\r
+--| COMPONENTS |\r
+--+-----------------------------------------------------------------------------+\r
+\r
+component pci32tlite\r
+port (\r
+\r
+ -- General \r
+ clk33 : in std_logic;\r
+ nrst : in std_logic;\r
+ \r
+ -- PCI target 32bits\r
+ ad : inout std_logic_vector(31 downto 0);\r
+ cbe : in std_logic_vector(3 downto 0);\r
+ par : out std_logic; \r
+ frame : in std_logic;\r
+ irdy : in std_logic;\r
+ trdy : out std_logic;\r
+ devsel : out std_logic;\r
+ stop : out std_logic;\r
+ idsel : in std_logic;\r
+ perr : out std_logic;\r
+ serr : out std_logic;\r
+ intb : out std_logic;\r
+ \r
+ -- Master whisbone\r
+ wb_adr_o : out std_logic_vector(24 downto 1); \r
+ wb_dat_i : in std_logic_vector(15 downto 0);\r
+ wb_dat_o : out std_logic_vector(15 downto 0);\r
+ wb_sel_o : out std_logic_vector(1 downto 0);\r
+ wb_we_o : out std_logic;\r
+ wb_stb_o : out std_logic;\r
+ wb_cyc_o : out std_logic;\r
+ wb_ack_i : in std_logic;\r
+ wb_err_i : in std_logic;\r
+ wb_int_i : in std_logic;\r
+\r
+ -- debug signals\r
+ debug_init : out std_logic;\r
+ debug_access : out std_logic \r
+\r
+ );\r
+end component;\r
+\r
+component heartbeat\r
+port (\r
+ clk_i : in std_logic;\r
+ nrst_i : in std_logic;\r
+ led2_o : out std_logic;\r
+ led3_o : out std_logic;\r
+ led4_o : out std_logic;\r
+ led5_o : out std_logic\r
+);\r
+end component;\r
+\r
+\r
+--+-----------------------------------------------------------------------------+\r
+--| CONSTANTS |\r
+--+-----------------------------------------------------------------------------+\r
+--+-----------------------------------------------------------------------------+\r
+--| SIGNALS |\r
+--+-----------------------------------------------------------------------------+\r
+\r
+ signal wb_adr : std_logic_vector(24 downto 1); \r
+ signal wb_dat_out : std_logic_vector(15 downto 0);\r
+ signal wb_dat_in : std_logic_vector(15 downto 0);\r
+ signal wb_sel : std_logic_vector(1 downto 0);\r
+ signal wb_we : std_logic;\r
+ signal wb_stb : std_logic;\r
+ signal wb_cyc : std_logic;\r
+ signal wb_ack : std_logic;\r
+ signal wb_err : std_logic;\r
+ signal wb_int : std_logic;\r
+\r
+\r
+begin\r
+\r
+--+-----------------------------------------+\r
+--| PCI Target |\r
+--+-----------------------------------------+\r
+\r
+u_pci: component pci32tlite\r
+port map(\r
+ clk33 => PCI_CLK,\r
+ nrst => PCI_nRES,\r
+ ad => PCI_AD,\r
+ cbe => PCI_CBE,\r
+ par => PCI_PAR,\r
+ frame => PCI_nFRAME,\r
+ irdy => PCI_nIRDY,\r
+ trdy => PCI_nTRDY,\r
+ devsel => PCI_nDEVSEL,\r
+ stop => PCI_nSTOP,\r
+ idsel => PCI_IDSEL,\r
+ perr => PCI_nPERR,\r
+ serr => PCI_nSERR,\r
+ intb => PCI_nINT,\r
+ wb_adr_o => wb_adr, \r
+ wb_dat_i => wb_dat_out,\r
+ wb_dat_o => wb_dat_in,\r
+ wb_sel_o => wb_sel, \r
+ wb_we_o => wb_we,\r
+ wb_stb_o => wb_stb, \r
+ wb_cyc_o => wb_cyc,\r
+ wb_ack_i => wb_ack,\r
+ wb_err_i => wb_err,\r
+ wb_int_i => wb_int\r
+-- debug_init => LED3,\r
+-- debug_access => LED2\r
+ );\r
+\r
+--+-----------------------------------------+\r
+--| WB-7seg |\r
+--+-----------------------------------------+\r
+\r
+my_heartbeat: component heartbeat\r
+port map( \r
+ clk_i => PCI_CLK,\r
+ nrst_i => PCI_nRES,\r
+ led2_o => LED2,\r
+ led3_o => LED3,\r
+ led4_o => LED4,\r
+ led5_o => LED5\r
+);\r
+\r
+end dhwk_arch;\r
projects / raggedstone / blobdiff