add sources for ide daughterboard cpld

[raggedstone] / ideboard / ideboard.ucf

diff --git a/ideboard/ideboard.ucf b/ideboard/ideboard.ucf
new file mode 100644 (file)
index 0000000..b9e6835
--- /dev/null
+++ b/ideboard/ideboard.ucf
@@ -0,0 +1,71 @@
+NET "LED_1"            LOC = "P70" ;
+NET "LED_2"            LOC = "P68" ;
+NET "LED_3"            LOC = "P67" ;
+NET "LED_4"            LOC = "P66" ;
+NET "IDE_DATA<0>"      LOC = "P91" ;
+NET "IDE_DATA<1>"      LOC = "P93" ;
+NET "IDE_DATA<2>"      LOC = "P95" ;
+NET "IDE_DATA<3>"      LOC = "P97" ;
+NET "IDE_DATA<4>"      LOC = "P1" ;
+NET "IDE_DATA<5>"      LOC = "P4" ;
+NET "IDE_DATA<6>"      LOC = "P8" ;
+NET "IDE_DATA<7>"      LOC = "P10" ;
+NET "IDE_DATA<8>"      LOC = "P11" ;
+NET "IDE_DATA<9>"      LOC = "P9" ;
+NET "IDE_DATA<10>"     LOC = "P6" ;
+NET "IDE_DATA<11>"     LOC = "P3" ;
+NET "IDE_DATA<12>"     LOC = "P99" ;
+NET "IDE_DATA<13>"     LOC = "P96" ;
+NET "IDE_DATA<14>"     LOC = "P94" ;
+NET "IDE_DATA<15>"     LOC = "P92" ;
+NET "IDE_ADDR<0>"      LOC = "P77" ;
+NET "IDE_ADDR<1>"      LOC = "P78" ;
+NET "IDE_ADDR<2>"      LOC = "P76" ;
+NET "IDE_RESET"                LOC = "P12" ;
+NET "IDE_IO_READ"      LOC = "P87" ;
+NET "IDE_GPIO_DMA66_DETECT"    LOC = "P79" ;
+NET "IDE_DDRQ"         LOC = "P90" ;
+NET "IDE_CABLE_SELECT" LOC = "P86" ;
+NET "IDE_IO_WRITE"     LOC = "P89" ;
+NET "IDE_IOC_HRDY"     LOC = "P85" ;
+NET "IDE_DDACK"                LOC = "P82" ;
+NET "IDE_CHIP_SELECT_1P"       LOC = "P72" ;
+NET "IDE_CHIP_SELECT_3P"       LOC = "P74" ;
+NET "IDE_IRQ"          LOC = "P81" ;
+NET "IDE_ACTIVITY"     LOC = "P71" ;
+NET "FPGA1"            LOC = "P65" ;
+NET "FPGA2"            LOC = "P59" ;
+NET "FPGA3"            LOC = "P58" ;
+NET "FPGA4"            LOC = "P64" ;
+NET "FPGA5"            LOC = "P63" ;
+NET "FPGA6"            LOC = "P61" ;
+NET "FPGA7"            LOC = "P60" ;
+NET "FPGA8"            LOC = "P42" ;
+NET "FPGA9"            LOC = "P22" ;
+NET "FPGA10"           LOC = "P17" ;
+NET "FPGA11"           LOC = "P15" ;
+NET "FPGA12"           LOC = "P14" ;
+NET "FPGA13"           LOC = "P20" ;
+NET "FPGA14"           LOC = "P18" ;
+NET "FPGA15"           LOC = "P13" ;
+NET "FPGA16"           LOC = "P16" ;
+NET "OUT1"             LOC = "P56" ;
+NET "OUT2"             LOC = "P54" ;
+NET "OUT3"             LOC = "P52" ;
+NET "OUT4"             LOC = "P49" ;
+NET "OUT5"             LOC = "P41" ;
+NET "OUT6"             LOC = "P39" ;
+NET "OUT7"             LOC = "P37" ;
+NET "OUT8"             LOC = "P35" ;
+NET "OUT9"             LOC = "P32" ;
+NET "OUT10"            LOC = "P30" ;
+NET "OUT11"            LOC = "P29" ;
+NET "OUT12"            LOC = "P27" ;
+NET "OUT13"            LOC = "P36" ;
+NET "OUT14"            LOC = "P33" ;
+NET "OUT15"            LOC = "P28" ;
+NET "OUT16"            LOC = "P25" ;
+NET "OUT17"            LOC = "P40" ;
+NET "OUT18"            LOC = "P53" ;
+NET "OUT19"            LOC = "P50" ;
+NET "OUT20"            LOC = "P55" ;