Update ChipScope coregeneration to coregen as used in ISE Design Suite 10.1

[raggedstone] / dhwk / vio.arg

diff --git a/dhwk/vio.arg b/dhwk/vio.arg
deleted file mode 100644 (file)
index 44f7884..0000000
--- a/dhwk/vio.arg
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# Usage: generate.exe vio -f=<arg_file_name>
-#
--compname=vio
--outputdirectory=.
--devicefamily=Spartan3
--srl16type=2
--asyncoutwidth=1
--createcdc