--- J.STELZNER\r
--- INFORMATIK-3 LABOR\r
--- 23.08.2006\r
--- File: CONNECTING_FSM.VHD\r
-\r
-library ieee ;\r
-use ieee.std_logic_1164.all ;\r
-\r
-entity CONNECTING_FSM is\r
- port\r
- (\r
- PCI_CLOCK :in std_logic; \r
- RESET :in std_logic; \r
- PSC_ENABLE :in std_logic;\r
- SYNC_S_FIFO_EFn :in std_logic;\r
- SPC_ENABLE :in std_logic;\r
- SYNC_R_FIFO_FFn :in std_logic;\r
- S_FIFO_Q_OUT :in std_logic_vector(7 downto 0);\r
- S_FIFO_READn :out std_logic;\r
- R_FIFO_WRITEn :out std_logic;\r
- R_FIFO_D_IN :out std_logic_vector(7 downto 0) \r
- );\r
-end entity CONNECTING_FSM;\r
-\r
-architecture CONNECTING_FSM_DESIGN of CONNECTING_FSM is\r
-\r
- signal REG :std_logic_vector(7 downto 0);\r
- signal HELP_0,HELP_1 :std_logic;\r
- signal SIG_LOAD :std_logic;\r
-\r
-\r
---**********************************************************\r
---*** CONNECTING FSM CODIERUNG ***\r
---**********************************************************\r
---\r
---\r
--- ---------- HELP_0\r
--- |--------- HELP_1 \r
--- ||-------- LOAD \r
--- |||------- WRITE \r
--- ||||------ READ \r
--- ||||| \r
- constant S0 :std_logic_vector(4 downto 0) := "00011";--\r
- constant S1 :std_logic_vector(4 downto 0) := "01010";--READ\r
- constant S2 :std_logic_vector(4 downto 0) := "10010";--READ\r
- constant S3 :std_logic_vector(4 downto 0) := "11110";--READ,LOAD\r
- constant S4 :std_logic_vector(4 downto 0) := "11011";--\r
- constant S5 :std_logic_vector(4 downto 0) := "01001";--WRITE\r
- constant S6 :std_logic_vector(4 downto 0) := "10001";--WRITE\r
- constant S7 :std_logic_vector(4 downto 0) := "11001";--WRITE\r
-\r
- signal STATES :std_logic_vector(4 downto 0);\r
-\r
---************************************************************\r
---*** FSM SPEICHER-AUTOMAT ***\r
---************************************************************\r
-\r
- attribute syn_state_machine : boolean;\r
- attribute syn_state_machine of STATES : signal is false;\r
-\r
---************************************************************\r
---*** REGISTER BESCHREIBUNG ***\r
---************************************************************\r
-\r
-begin\r
-\r
- process (PCI_CLOCK) \r
- begin\r
- if (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
- if SIG_LOAD = '1' then REG <= S_FIFO_Q_OUT;\r
- elsif SIG_LOAD = '0' then REG <= REG; \r
- end if;\r
- end if;\r
- end process;\r
-\r
---************************************************************\r
---*** FSM BESCHREIBUNG ***\r
---************************************************************\r
-\r
- process (PCI_CLOCK)\r
- begin \r
- if (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
- \r
- if RESET = '1' then STATES <= S0;\r
- else\r
- \r
- case STATES is\r
-\r
- when S0 => \r
- if PSC_ENABLE = '1' and\r
- SPC_ENABLE = '1' and\r
- SYNC_S_FIFO_EFn = '1' then\r
-\r
- STATES <= S1;\r
- else \r
- STATES <= S0;\r
- end if;\r
-\r
- when S1 => STATES <= S2;\r
- when S2 => STATES <= S3;\r
- when S3 => STATES <= S4;\r
-\r
- when S4 => \r
- if SYNC_R_FIFO_FFn = '1' then\r
-\r
- STATES <= S5;\r
- else \r
- STATES <= S4;\r
- end if;\r
-\r
- when S5 => STATES <= S6;\r
- when S6 => STATES <= S7;\r
- when S7 => STATES <= S0;\r
-\r
- when others => \r
-\r
- STATES <= S0; \r
-\r
- end case; -- STATES \r
- end if; -- RESET \r
- end if; -- PCI_CLOCK \r
- end process; -- PROCESS\r
-\r
---************************************************************\r
---*** ZUWEISUNG signal/out <= STATES ***\r
---************************************************************\r
-\r
- HELP_0 <= STATES(4); \r
- HELP_1 <= STATES(3);\r
- SIG_LOAD <= STATES(2);\r
- R_FIFO_WRITEn <= STATES(1);\r
- S_FIFO_READn <= STATES(0);\r
-\r
- R_FIFO_D_IN <= REG;\r
-\r
-end architecture CONNECTING_FSM_DESIGN;\r
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: CONNECTING_FSM.VHD
+
+library ieee ;
+use ieee.std_logic_1164.all ;
+
+entity CONNECTING_FSM is
+ port
+ (
+ PCI_CLOCK :in std_logic;
+ RESET :in std_logic;
+ PSC_ENABLE :in std_logic;
+ SYNC_S_FIFO_EFn :in std_logic;
+ SPC_ENABLE :in std_logic;
+ SYNC_R_FIFO_FFn :in std_logic;
+ S_FIFO_Q_OUT :in std_logic_vector(7 downto 0);
+ S_FIFO_READn :out std_logic;
+ R_FIFO_WRITEn :out std_logic;
+ R_FIFO_D_IN :out std_logic_vector(7 downto 0)
+ );
+end entity CONNECTING_FSM;
+
+architecture CONNECTING_FSM_DESIGN of CONNECTING_FSM is
+
+ signal REG :std_logic_vector(7 downto 0);
+ signal HELP_0,HELP_1 :std_logic;
+ signal SIG_LOAD :std_logic;
+
+
+--**********************************************************
+--*** CONNECTING FSM CODIERUNG ***
+--**********************************************************
+--
+--
+-- ---------- HELP_0
+-- |--------- HELP_1
+-- ||-------- LOAD
+-- |||------- WRITE
+-- ||||------ READ
+-- |||||
+ constant S0 :std_logic_vector(4 downto 0) := "00011";--
+ constant S1 :std_logic_vector(4 downto 0) := "01010";--READ
+ constant S2 :std_logic_vector(4 downto 0) := "10010";--READ
+ constant S3 :std_logic_vector(4 downto 0) := "11110";--READ,LOAD
+ constant S4 :std_logic_vector(4 downto 0) := "11011";--
+ constant S5 :std_logic_vector(4 downto 0) := "01001";--WRITE
+ constant S6 :std_logic_vector(4 downto 0) := "10001";--WRITE
+ constant S7 :std_logic_vector(4 downto 0) := "11001";--WRITE
+
+ signal STATES :std_logic_vector(4 downto 0);
+
+--************************************************************
+--*** FSM SPEICHER-AUTOMAT ***
+--************************************************************
+
+ attribute syn_state_machine : boolean;
+ attribute syn_state_machine of STATES : signal is false;
+
+--************************************************************
+--*** REGISTER BESCHREIBUNG ***
+--************************************************************
+
+begin
+
+ process (PCI_CLOCK)
+ begin
+ if (PCI_CLOCK'event and PCI_CLOCK = '1') then
+ if SIG_LOAD = '1' then REG <= S_FIFO_Q_OUT;
+ elsif SIG_LOAD = '0' then REG <= REG;
+ end if;
+ end if;
+ end process;
+
+--************************************************************
+--*** FSM BESCHREIBUNG ***
+--************************************************************
+
+ process (PCI_CLOCK)
+ begin
+ if (PCI_CLOCK'event and PCI_CLOCK = '1') then
+
+ if RESET = '1' then STATES <= S0;
+ else
+
+ case STATES is
+
+ when S0 =>
+ if PSC_ENABLE = '1' and
+ SPC_ENABLE = '1' and
+ SYNC_S_FIFO_EFn = '1' then
+
+ STATES <= S1;
+ else
+ STATES <= S0;
+ end if;
+
+ when S1 => STATES <= S2;
+ when S2 => STATES <= S3;
+ when S3 => STATES <= S4;
+
+ when S4 =>
+ if SYNC_R_FIFO_FFn = '1' then
+
+ STATES <= S5;
+ else
+ STATES <= S4;
+ end if;
+
+ when S5 => STATES <= S6;
+ when S6 => STATES <= S7;
+ when S7 => STATES <= S0;
+
+ when others =>
+
+ STATES <= S0;
+
+ end case; -- STATES
+ end if; -- RESET
+ end if; -- PCI_CLOCK
+ end process; -- PROCESS
+
+--************************************************************
+--*** ZUWEISUNG signal/out <= STATES ***
+--************************************************************
+
+ HELP_0 <= STATES(4);
+ HELP_1 <= STATES(3);
+ SIG_LOAD <= STATES(2);
+ R_FIFO_WRITEn <= STATES(1);
+ S_FIFO_READn <= STATES(0);
+
+ R_FIFO_D_IN <= REG;
+
+end architecture CONNECTING_FSM_DESIGN;
projects / raggedstone / blobdiff