+= read registers from userland

[raggedstone] / dhwk / source / pci / top.vhd

diff --git a/dhwk/source/pci/top.vhd b/dhwk/source/pci/top.vhd
index 27cd84c8b0f12855e72ae174ceb00f8e5c5e199c..5c4851a120556bd99c8001153b8b5aa403479ac5 100644 (file)
--- a/dhwk/source/pci/top.vhd
+++ b/dhwk/source/pci/top.vhd
@@ -90,6 +90,7 @@ architecture SCHEMATIC of dhwk is
         signal SPC_RDY_IN : std_logic;
         signal SERIAL_OUT : std_logic;
         signal SPC_RDY_OUT : std_logic;
         signal SPC_RDY_IN : std_logic;
         signal SERIAL_OUT : std_logic;
         signal SPC_RDY_OUT : std_logic;

+        signal led_PCI_INTA : std_logic;

         signal watch_PCI_INTAn : std_logic;
         signal watch_PCI_TRDYn : std_logic;
         signal watch_PCI_STOPn : std_logic;
         signal watch_PCI_INTAn : std_logic;
         signal watch_PCI_TRDYn : std_logic;
         signal watch_PCI_STOPn : std_logic;


@@ -100,7 +101,8 @@ architecture SCHEMATIC of dhwk is
         signal control1 : std_logic_vector(35 downto 0);
         signal data : std_logic_vector(95 downto 0);
         signal trig0 : std_logic_vector(31 downto 0);
         signal control1 : std_logic_vector(35 downto 0);
         signal data : std_logic_vector(95 downto 0);
         signal trig0 : std_logic_vector(31 downto 0);

-       signal vio_async_out : std_logic_vector(0 downto 0);
+       signal vio_sync_out : std_logic_vector(0 downto 0);
+       signal vio_async_in : std_logic_vector(3 downto 0);

 
         component MESS_1_TB
                 Port ( DEVSELn : In std_logic;
 
         component MESS_1_TB
                 Port ( DEVSELn : In std_logic;


@@ -253,20 +255,36 @@ architecture SCHEMATIC of dhwk is
                port
                (
                        control : in std_logic_vector(35 downto 0);
                port
                (
                        control : in std_logic_vector(35 downto 0);

-                       async_out : out std_logic_vector(0 downto 0)
+                       clk : in std_logic;
+                       async_in : in std_logic_vector(3 downto 0);
+                       sync_out : out std_logic_vector(0 downto 0)

                );
        end component;
 
 
 begin
                );
        end component;
 
 
 begin

+       process(PCI_CLOCK)
+       begin
+               if rising_edge(PCI_CLOCK) then
+                       led_PCI_INTA <= not (watch_PCI_INTAn and (not vio_sync_out(0)));
+               end if;
+       end process;
+

         watch_PCI_REQn <= '1';
         SERIAL_IN <= SERIAL_OUT;
         SPC_RDY_IN <= SPC_RDY_OUT;
         LED_2 <= not PCI_RSTn;
         LED_3 <= not PCI_IDSEL;
         LED_4 <= not PCI_FRAMEn;
         watch_PCI_REQn <= '1';
         SERIAL_IN <= SERIAL_OUT;
         SPC_RDY_IN <= SPC_RDY_OUT;
         LED_2 <= not PCI_RSTn;
         LED_3 <= not PCI_IDSEL;
         LED_4 <= not PCI_FRAMEn;

-        LED_5 <= not (watch_PCI_INTAn and (not vio_async_out(0)));
-        PCI_INTAn <= watch_PCI_INTAn and (not vio_async_out(0));
+       LED_5 <= led_PCI_INTA;
+        PCI_INTAn <= (watch_PCI_INTAn and (not vio_sync_out(0)));
+
+       vio_async_in(3 downto 0) <= (
+       0 => not PCI_RSTn,
+       1 => not PCI_IDSEL,
+       2 => not PCI_FRAMEn,
+       3 => led_PCI_INTA
+       );

 
         trig0(31 downto 0) <= (
         0 => watch_PCI_INTAn,
 
         trig0(31 downto 0) <= (
         0 => watch_PCI_INTAn,


@@ -441,6 +459,8 @@ begin
        port map
        (
                control => control1,
        port map
        (
                control => control1,

-               async_out => vio_async_out
+               clk => PCI_CLOCK,
+               async_in => vio_async_in,
+               sync_out => vio_sync_out

        );
 end SCHEMATIC;
        );
 end SCHEMATIC;