Update ChipScope coregeneration to coregen as used in ISE Design Suite 10.1

[raggedstone] / ethernet / Makefile

diff --git a/ethernet/Makefile b/ethernet/Makefile
index d02d65d8aa87d89caed4cb7651225c148d17639c..e8a70313a0133ab59e0899fb6c40250cf813bb4f 100644 (file)
--- a/ethernet/Makefile
+++ b/ethernet/Makefile
@@ -1,3 +1,16 @@
 PROJECT := ethernet
+CLEANFILES := param.opt icon.vhd icon.vho icon_flist.txt icon_readme.txt icon_xmdf.tcl ila.vhd ila.vho ila_flist.txt ila_readme.txt ila_xmdf.tcl
+
+ethernet_all: ip all
+
+ip: icon.ngc ila.ngc
+
+icon.ngc: icon.xco
+       coregen -b $<
+       -rmdir -p tmp/_cg
+
+ila.ngc: ila.xco
+       coregen -b $<
+       -rmdir -p tmp/_cg
 
 include ../common/Makefile.common