WISHBONE B3

[raggedstone] / ethernet / source / top.vhd

diff --git a/ethernet/source/top.vhd b/ethernet/source/top.vhd
index 05412220f19ed50fd14f1b5b09ab8f81af9f2867..68188ac8926d666474c85a3f4144045099621b22 100644 (file)
--- a/ethernet/source/top.vhd
+++ b/ethernet/source/top.vhd
@@ -72,6 +72,8 @@ PORT(
         mdc_pad_o : OUT std_logic;
         md_pad_o : OUT std_logic;
         md_padoe_o : OUT std_logic;
+        m_wb_cti_o : OUT std_logic_vector(2 downto 0);
+        m_wb_bte_o : OUT std_logic_vector(1 downto 0);
         int_o : OUT std_logic
         );
 END COMPONENT;
@@ -202,6 +204,9 @@ signal md_padoe_o : std_logic;
 signal int_o : std_logic;
 signal wbm_adr_o : std_logic_vector(31 downto 0);
 
+signal m_wb_cti_o : std_logic_vector(2 downto 0);
+signal m_wb_bte_o : std_logic_vector(1 downto 0);
+
 BEGIN
 
 PCI_RSTn    <= pci_rst_o    when (pci_rst_oe_o = '1')     else 'Z';
@@ -240,8 +245,8 @@ Inst_pci_bridge32: pci_bridge32 PORT MAP(
         wbs_cyc_i => m_wb_cyc_o,
         wbs_stb_i => m_wb_stb_o,
         wbs_we_i => m_wb_we_o,
-        wbs_cti_i => (others => '0'),
-        wbs_bte_i => (others => '0'),
+        wbs_cti_i => m_wb_cti_o,
+        wbs_bte_i => m_wb_bte_o,
         wbs_ack_o => m_wb_ack_i,
         -- wbs_rty_o => ,
         wbs_err_o => m_wb_err_i,
@@ -334,6 +339,8 @@ Inst_eth_top: eth_top PORT MAP(
         md_pad_i => MD_PAD_IO,
         md_pad_o => md_pad_o,
         md_padoe_o => md_padoe_o,
+        m_wb_cti_o => m_wb_cti_o,
+        m_wb_bte_o => m_wb_bte_o, 
         int_o => int_o
 );