CBEn

[raggedstone] / dhwk / source / top.vhd

diff --git a/dhwk/source/top.vhd b/dhwk/source/top.vhd
index 4becb68de5b660595716589d730a2a40835bba91..971b0c49c2104a6b98022a6ff57f6a4cfca2cff5 100644 (file)
--- a/dhwk/source/top.vhd
+++ b/dhwk/source/top.vhd
@@ -92,8 +92,8 @@ architecture SCHEMATIC of dhwk is
    signal SPC_RDY_OUT : std_logic;\r
    signal watch : std_logic;\r
    signal control0       : std_logic_vector(35 downto 0);\r
-   signal data       : std_logic_vector(35 downto 0);\r
-   signal trig0      : std_logic_vector(7 downto 0);\r
+   signal data       : std_logic_vector(95 downto 0);\r
+   signal trig0      : std_logic_vector(31 downto 0);\r
 \r
    component MESS_1_TB\r
       Port ( DEVSELn : In    std_logic;\r
@@ -236,8 +236,8 @@ end component;
     (\r
       control     : in    std_logic_vector(35 downto 0);\r
       clk         : in    std_logic;\r
-      data        : in    std_logic_vector(35 downto 0);\r
-      trig0       : in    std_logic_vector(7 downto 0)\r
+      data        : in    std_logic_vector(95 downto 0);\r
+      trig0       : in    std_logic_vector(31 downto 0)\r
     );\r
   end component;\r
 \r
@@ -250,7 +250,7 @@ begin
        LED_4 <= '0';\r
        LED_5 <= not watch;\r
        PCI_INTAn <= watch;\r
-       trig0(7 downto 0) <= (0 => watch, 1 => R_FIFO_READn, 2 => R_FIFO_WRITEn, 3 => S_FIFO_READn, 4 => S_FIFO_WRITEn, others => '0');\r
+       trig0(31 downto 0) <= (0 => watch, 1 => R_FIFO_READn, 2 => R_FIFO_WRITEn, 3 => S_FIFO_READn, 4 => S_FIFO_WRITEn, others => '0');\r
        data(0) <= watch;\r
        \r
        data(1) <= R_EFn;\r
@@ -273,6 +273,8 @@ begin
        data(18) <= SPC_RDY_OUT;\r
        data(26 downto 19) <= S_FIFO_Q_OUT;\r
        data(34 downto 27) <= R_FIFO_Q_OUT;\r
+       data(66 downto 35) <= PCI_AD(31 downto 0);\r
+       data(70 downto 67) <= PCI_CBEn(3 downto 0);\r
 \r
    I19 : MESS_1_TB\r
       Port Map ( DEVSELn=>DEVSELn, INTAn=>INTAn, KONST_1=>KONST_1,\r