connect LEDs on IDE board to main FPGA and let them blink

[raggedstone] / heartbeat / source / heartbeat.vhd

diff --git a/heartbeat/source/heartbeat.vhd b/heartbeat/source/heartbeat.vhd
index a1a181fa7bff4f971438d36f4f1f481375cc07fb..cae72cd9a4e4f6042fa4cac8a6a5647e8f26e0cc 100644 (file)
--- a/heartbeat/source/heartbeat.vhd
+++ b/heartbeat/source/heartbeat.vhd
@@ -14,7 +14,11 @@ port (
        led2_o : out std_logic;
        led3_o : out std_logic;
        led4_o : out std_logic;
-       led5_o : out std_logic
+       led5_o : out std_logic;
+       led6_o : out std_logic;
+       led7_o : out std_logic;
+       led8_o : out std_logic;
+       led9_o : out std_logic
 );   
 
 end heartbeat;
@@ -24,11 +28,11 @@ begin
 
 process(clk_i, nrst_i)
 variable counter : std_logic_vector(31 downto 0);
-variable state : std_logic_vector(3 downto 0) := "0001";
+variable state : std_logic_vector(7 downto 0) := "00000001";
 variable direction : std_logic := '0';
 begin
 
-if (clk_i'event AND clk_i = '1') then
+if (rising_edge(clk_i)) then
        if nrst_i = '0' then
                counter := (others => '0');
         else
@@ -36,9 +40,13 @@ if (clk_i'event AND clk_i = '1') then
                led3_o <= state(1);
                led4_o <= state(2);
                led5_o <= state(3);
+               led6_o <= state(4);
+               led7_o <= state(5);
+               led8_o <= state(6);
+               led9_o <= state(7);
                counter := counter + 1;
                if counter = divider then
-                       if state(3) = '1' then
+                       if state(7) = '1' then
                                direction := '1';
                        end if;
 
@@ -47,11 +55,11 @@ if (clk_i'event AND clk_i = '1') then
                        end if;
 
                        if direction = '0' then
-                               state(3 downto 1) := state(2 downto 0);
+                               state(7 downto 1) := state(6 downto 0);
                                state(0) := '0';
                        else
-                               state(2 downto 0) := state(3 downto 1);
-                               state(3) := '0';
+                               state(6 downto 0) := state(7 downto 1);
+                               state(7) := '0';
                        end if;
                        counter := (others => '0');
                end if;