);\r
end component;\r
\r
+component generic_fifo_sc_a\r
+port (\r
+ clk : in std_logic;\r
+ rst : in std_logic;\r
+ clr : in std_logic;\r
+ din : in std_logic_vector(7 downto 0);\r
+ we : in std_logic;\r
+ dout : out std_logic_vector(7 downto 0);\r
+ re : in std_logic;\r
+ full : out std_logic;\r
+ full_r : out std_logic;\r
+ empty : out std_logic;\r
+ empty_r : out std_logic;\r
+ full_n : out std_logic;\r
+ full_n_r : out std_logic;\r
+ empty_n : out std_logic;\r
+ empty_n_r : out std_logic;\r
+ level : out std_logic_vector(1 downto 0)\r
+);\r
+end component;\r
+\r
+component generic_dpram\r
+port (\r
+ rclk : in std_logic;\r
+ rrst : in std_logic;\r
+ rce : in std_logic;\r
+ oe : in std_logic;\r
+ raddr : in std_logic_vector(11 downto 0);\r
+ do : out std_logic_vector(7 downto 0);\r
+ wclk : in std_logic;\r
+ wrst : in std_logic;\r
+ wce : in std_logic;\r
+ we : in std_logic;\r
+ waddr : in std_logic_vector(11 downto 0);\r
+ di : in std_logic_vector(7 downto 0)\r
+);\r
+end component;\r
+\r
\r
--+-----------------------------------------------------------------------------+\r
--| CONSTANTS |\r