---+-------------------------------------------------------------------------------------------------+\r
---| |\r
---| File: top.vhd |\r
---| |\r
---| Components: pci32lite.vhd |\r
---| pciwbsequ.vhd |\r
---| pcidmux.vhd |\r
---| pciregs.vhd |\r
---| pcipargen.vhd |\r
---| -- Libs -- |\r
---| ona.vhd |\r
---| |\r
---| Description: RS1 PCI Demo : (TOP) Main file. |\r
---| |\r
---| |\r
---| |\r
---+-------------------------------------------------------------------------------------------------+\r
---| |\r
---| Revision history : |\r
---| Date Version Author Description |\r
---| |\r
---| |\r
---| To do: |\r
---| |\r
---+-------------------------------------------------------------------------------------------------+\r
-\r
-\r
---+-----------------------------------------------------------------------------+\r
---| LIBRARIES |\r
---+-----------------------------------------------------------------------------+\r
-\r
library ieee;\r
use ieee.std_logic_1164.all;\r
use ieee.std_logic_arith.all;\r
use ieee.std_logic_unsigned.all;\r
\r
---+-----------------------------------------------------------------------------+\r
---| ENTITY |\r
---+-----------------------------------------------------------------------------+\r
-\r
entity dhwk is\r
port (\r
\r
end dhwk;\r
\r
\r
---+-----------------------------------------------------------------------------+\r
---| ARCHITECTURE |\r
---+-----------------------------------------------------------------------------+\r
-\r
architecture dhwk_arch of dhwk is\r
\r
\r
---+-----------------------------------------------------------------------------+\r
---| COMPONENTS |\r
---+-----------------------------------------------------------------------------+\r
-\r
component pci32tlite\r
port (\r
\r
);\r
end component;\r
\r
+component generic_fifo_sc_a\r
+port (\r
+ clk : in std_logic;\r
+ rst : in std_logic;\r
+ clr : in std_logic;\r
+ din : in std_logic_vector(7 downto 0);\r
+ we : in std_logic;\r
+ dout : out std_logic_vector(7 downto 0);\r
+ re : in std_logic;\r
+ full : out std_logic;\r
+ full_r : out std_logic;\r
+ empty : out std_logic;\r
+ empty_r : out std_logic;\r
+ full_n : out std_logic;\r
+ full_n_r : out std_logic;\r
+ empty_n : out std_logic;\r
+ empty_n_r : out std_logic;\r
+ level : out std_logic_vector(1 downto 0)\r
+);\r
+end component;\r
\r
---+-----------------------------------------------------------------------------+\r
---| CONSTANTS |\r
---+-----------------------------------------------------------------------------+\r
---+-----------------------------------------------------------------------------+\r
---| SIGNALS |\r
---+-----------------------------------------------------------------------------+\r
+component wb_fifo\r
+port (\r
+ clk_i : in std_logic;\r
+ nrst_i : in std_logic;\r
+ \r
+ wb_adr_i : in std_logic_vector(24 downto 1);\r
+ wb_dat_o : out std_logic_vector(15 downto 0);\r
+ wb_dat_i : in std_logic_vector(15 downto 0);\r
+ wb_sel_i : in std_logic_vector(1 downto 0);\r
+ wb_we_i : in std_logic;\r
+ wb_stb_i : in std_logic;\r
+ wb_cyc_i : in std_logic;\r
+ wb_ack_o : out std_logic;\r
+ wb_err_o : out std_logic;\r
+ wb_int_o : out std_logic;\r
+ \r
+ fifo_data_i : in std_logic_vector(7 downto 0);\r
+ fifo_data_o : out std_logic_vector(7 downto 0);\r
+\r
+ fifo_we_o : out std_logic;\r
+ fifo_re_o : out std_logic\r
+);\r
+end component;\r
\r
- signal wb_adr : std_logic_vector(24 downto 1); \r
- signal wb_dat_out : std_logic_vector(15 downto 0);\r
- signal wb_dat_in : std_logic_vector(15 downto 0);\r
- signal wb_sel : std_logic_vector(1 downto 0);\r
- signal wb_we : std_logic;\r
- signal wb_stb : std_logic;\r
- signal wb_cyc : std_logic;\r
- signal wb_ack : std_logic;\r
- signal wb_err : std_logic;\r
- signal wb_int : std_logic;\r
+signal wb_adr : std_logic_vector(24 downto 1); \r
+signal wb_dat_out : std_logic_vector(15 downto 0);\r
+signal wb_dat_in : std_logic_vector(15 downto 0);\r
+signal wb_sel : std_logic_vector(1 downto 0);\r
+signal wb_we : std_logic;\r
+signal wb_stb : std_logic;\r
+signal wb_cyc : std_logic;\r
+signal wb_ack : std_logic;\r
+signal wb_err : std_logic;\r
+signal wb_int : std_logic;\r
+\r
+signal fifo_din : std_logic_vector(7 downto 0);\r
+signal fifo_dout : std_logic_vector(7 downto 0);\r
+signal fifo_we : std_logic;\r
+signal fifo_re : std_logic;\r
\r
\r
-begin\r
\r
---+-----------------------------------------+\r
---| PCI Target |\r
---+-----------------------------------------+\r
+begin\r
\r
u_pci: component pci32tlite\r
port map(\r
wb_int_i => wb_int\r
-- debug_init => LED3,\r
-- debug_access => LED2\r
- );\r
+);\r
\r
---+-----------------------------------------+\r
---| WB-7seg |\r
---+-----------------------------------------+\r
+my_generic_fifo: component generic_fifo_sc_a\r
+port map(\r
+ clk => PCI_CLK,\r
+ rst => PCI_nRES,\r
+ clr => '0',\r
+ din => fifo_din,\r
+ we => fifo_we,\r
+ dout => fifo_dout,\r
+ re => fifo_re\r
+-- full => ,\r
+-- full_r => ,\r
+-- empty => ,\r
+-- empty_r => ,\r
+-- full_n => ,\r
+-- full_n_r => ,\r
+-- empty_n => ,\r
+-- empty_n_r => ,\r
+-- level => ,\r
+);\r
+\r
+my_fifo: component wb_fifo\r
+port map(\r
+ clk_i => PCI_CLK,\r
+ nrst_i => PCI_nRES,\r
+\r
+ wb_adr_i => wb_adr,\r
+ wb_dat_o => wb_dat_out,\r
+ wb_dat_i => wb_dat_in,\r
+ wb_sel_i => wb_sel,\r
+ wb_we_i => wb_we,\r
+ wb_stb_i => wb_stb,\r
+ wb_cyc_i => wb_cyc,\r
+ wb_ack_o => wb_ack,\r
+ wb_err_o => wb_err,\r
+ wb_int_o => wb_int,\r
+\r
+ fifo_data_i => fifo_dout,\r
+ fifo_data_o => fifo_din,\r
+\r
+ fifo_we_o => fifo_we,\r
+ fifo_re_o => fifo_re\r
+);\r
\r
my_heartbeat: component heartbeat\r
port map( \r
projects / raggedstone / blobdiff