Update to EDK 9.2

[raggedstone] / ideboard / source / ide.vhd

diff --git a/ideboard/source/ide.vhd b/ideboard/source/ide.vhd
index 20cc961409b7f23beba36de477b1b6244148e92f..3ddc5c173c38ae37c2ec22f7f868aff2289acb3f 100644 (file)
--- a/ideboard/source/ide.vhd
+++ b/ideboard/source/ide.vhd
@@ -46,10 +46,10 @@ entity ide is
           IDE_CHIP_SELECT_3P : out std_logic;
           IDE_IRQ : out std_logic;
           IDE_ACTIVITY : out std_logic;
-          FPGA1 : out std_logic;
-          FPGA2 : out std_logic;
-          FPGA3 : out std_logic;
-          FPGA4 : out std_logic;
+          FPGA1 : in std_logic;
+          FPGA2 : in std_logic;
+          FPGA3 : in std_logic;
+          FPGA4 : in std_logic;
           FPGA5 : out std_logic;
           FPGA6 : out std_logic;
           FPGA7 : out std_logic;
@@ -88,9 +88,9 @@ end ide;
 architecture Behavioral of ide is
 
 begin
-       LED_1 <= '1';
-       LED_2 <= '1';
-       LED_3 <= '1';
-       LED_4 <= '0';
+       LED_1 <= FPGA1;
+       LED_2 <= FPGA2;
+       LED_3 <= FPGA3;
+       LED_4 <= FPGA4;
 end Behavioral;