connect LEDs on IDE board to main FPGA and let them blink

[raggedstone] / heartbeat / source / top_raggedstone.vhd

diff --git a/heartbeat/source/top_raggedstone.vhd b/heartbeat/source/top_raggedstone.vhd
index b0739895d536833d7a1a5db286d478bb755cade8..c7982941f1283337f185315ab2d796ae4ec64273 100644 (file)
--- a/heartbeat/source/top_raggedstone.vhd
+++ b/heartbeat/source/top_raggedstone.vhd
@@ -63,7 +63,11 @@ port (
        LED3    : out std_logic;\r
        LED2    : out std_logic;\r
        LED4            : out std_logic;\r
-       LED5            : out std_logic\r
+       LED5            : out std_logic;\r
+       IDE1    : out std_logic;\r
+       IDE2    : out std_logic;\r
+       IDE3    : out std_logic;\r
+       IDE4    : out std_logic\r
 \r
 );\r
 end raggedstone;\r
@@ -127,7 +131,11 @@ port (
        led2_o : out std_logic;\r
        led3_o : out std_logic;\r
        led4_o : out std_logic;\r
-       led5_o : out std_logic\r
+       led5_o : out std_logic;\r
+       led6_o : out std_logic;\r
+       led7_o : out std_logic;\r
+       led8_o : out std_logic;\r
+       led9_o : out std_logic\r
 );\r
 end component;\r
 \r
@@ -198,7 +206,11 @@ port map(
        led2_o => LED2,\r
        led3_o => LED3,\r
        led4_o => LED4,\r
-       led5_o => LED5\r
+       led5_o => LED5,\r
+       led6_o => IDE1,\r
+       led7_o => IDE2,\r
+       led8_o => IDE3,\r
+       led9_o => IDE4\r
 );\r
 \r
 end raggedstone_arch;\r